cur_floor.v

用verilog写的电梯控制器

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    11:09:50 01/06/07
// Design Name:    
// Module Name:    Cur_floor
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module Cur_floor(floor_out,lift_info,clk,reset);
output [3:0] floor_out;
input clk,reset;
input [3:0] lift_info;

reg [3:0] floor;
reg [7:0] i;

assign floor_out = floor;
always @ (negedge reset or posedge clk )
begin

	if(!reset)begin floor = 1; i=0;end
	else 	if(lift_info == 4 ||lift_info == 0)
			 begin 
			 i=i+1;
			 if (i==10 && lift_info == 4)begin  floor = floor+1;	i=0;end
			 else if (i==10 && lift_info == 0)begin  floor = floor-1; i=0;end
			 end

end
endmodule