floor.v

用verilog写的电梯控制器

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    22:13:54 12/19/06
// Design Name:    
// Module Name:    floor
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module floor(floor_out0,floor_out1,floor_out2,floor_out3,floor_out4,floor_out5,floor_out6,floor_out7,
             floor_out8,floor_out9,floor_out10,floor_out11,floor_out12,floor_out13,floor_out14,
				 floor_out15,floor_address,up,down,clk,reset);
parameter width=8;

output[width-1:0] floor_out0;		//reg [width-1:0] floor_out0;
output[width-1:0] floor_out1;		//reg [width-1:0] floor_out1;
output[width-1:0] floor_out2;		//reg [width-1:0] floor_out2;
output[width-1:0] floor_out3;		// [width-1:0] floor_out3;
output[width-1:0] floor_out4;		//reg [width-1:0] floor_out4;
output[width-1:0] floor_out5;		//reg [width-1:0] floor_out5;
output[width-1:0] floor_out6;		//reg [width-1:0] floor_out6;
output[width-1:0] floor_out7;		//reg [width-1:0] floor_out7;
output[width-1:0] floor_out8;		//reg [width-1:0] floor_out8;
output[width-1:0] floor_out9;		//reg [width-1:0] floor_out9;
output[width-1:0] floor_out10;	//reg [width-1:0] floor_out10;
output[width-1:0] floor_out11;	//reg [width-1:0] floor_out11;
output[width-1:0] floor_out12;	//	reg [width-1:0] floor_out12;
output[width-1:0] floor_out13;	//reg [width-1:0] floor_out13;
output[width-1:0] floor_out14;	//	reg [width-1:0] floor_out14;
output[width-1:0] floor_out15;	//reg [width-1:0] floor_out15;



input up,down,clk,reset;
input [3:0] floor_address;



reg [width-5:0] register [15:0];		 // 每层楼的楼层状态字共八位，前四位表示楼层的地址，
                                     //后四位中，第一位表示当前楼层是否有电梯，第二位表示是否有													 //开始请求，第三位表示是否有向上请求，第四位表示是否有向下请求
reg [15:0] up_r,down_r,up_rr,down_rr;

assign floor_out0 ={register[0],1'b0,1'b0,~up_r[0]&up,~down_r[0]&down};
assign floor_out1 ={register[1],1'b0,1'b0,~up_r[1]&up,~down_r[1]&down};
assign floor_out2 ={register[2],1'b0,1'b0,~up_r[2]&up,~down_r[2]&down};
assign floor_out3 ={register[3],1'b0,1'b0,~up_r[3]&up,~down_r[3]&down};
assign floor_out4 ={register[4],1'b0,1'b0,~up_r[4]&up,~down_r[4]&down};
assign floor_out5 ={register[5],1'b0,1'b0,~up_r[5]&up,~down_r[5]&down};
assign floor_out6 ={register[6],1'b0,1'b0,~up_r[6]&up,~down_r[6]&down};
assign floor_out7 ={register[7],1'b0,1'b0,~up_r[7]&up,~down_r[7]&down};
assign floor_out8 ={register[8],1'b0,1'b0,~up_r[8]&up,~down_r[8]&down};
assign floor_out9 ={register[9],1'b0,1'b0,~up_r[9]&up,~down_r[9]&down};
assign floor_out10 ={register[10],1'b0,1'b0,~up_r[10]&up,~down_r[10]&down};
assign floor_out11 ={register[11],1'b0,1'b0,~up_r[11]&up,~down_r[11]&down};
assign floor_out12 ={register[12],1'b0,1'b0,~up_r[12]&up,~down_r[12]&down};
assign floor_out13 ={register[13],1'b0,1'b0,~up_r[13]&up,~down_r[13]&down};
assign floor_out14 ={register[14],1'b0,1'b0,~up_r[14]&up,~down_r[14]&down};
assign floor_out15 ={register[15],1'b0,1'b0,~up_r[15]&up,~down_r[15]&down};

always @(  negedge reset )
begin
    if(!reset)
      begin
        register[0]<='h0; 	
        register[1]<='h1;	
        register[2]<='h2;	 
        register[3]<='h3;	
        register[4]<='h4;	 
        register[5]<='h5;	 
        register[6]<='h6;	
        register[7]<='h7;	 
		  register[8]<='h8;	 
		  register[9]<='h9;	 
		  register[10]<='hA;	 
		  register[11]<='hB;	 
        register[12]<='hC;	 
        register[13]<='hD;	 
        register[14]<='hE;	 
        register[15]<='hF;	
		   
      end   
end



always @ ( negedge reset or posedge clk )
begin
  if(reset == 0 )begin  down_r <= 16'hffff; up_r<= 16'hffff;
                        down_rr <= 16'hffff; up_rr<= 16'hffff; end
     else 
	   begin 
      case(floor_address)
    	   'b0000:begin up_rr[0]<= up;up_r[0]<= up_rr[0];	down_rr[0]<=down;down_r[0]<=down_rr[0];end	
         'b0001:begin up_rr[1]<= up;up_r[1]<= up_rr[1];  down_rr[1]<=down;down_r[1]<=down_rr[1];end	
         'b0010:begin up_rr[2]<= up;up_r[2]<= up_rr[2];  down_rr[2]<=down;down_r[2]<=down_rr[2];end
         'b0011:begin up_rr[3]<= up;up_r[3]<= up_rr[3];  down_rr[3]<=down;down_r[3]<=down_rr[3];end
         'b0100:begin up_rr[4]<= up;up_r[4]<= up_rr[4];  down_rr[4]<=down;down_r[4]<=down_rr[4];end
         'b0101:begin up_rr[5]<= up;up_r[5]<= up_rr[5];  down_rr[5]<=down;down_r[5]<=down_rr[5];end
         'b0110:begin up_rr[6]<= up;up_r[6]<= up_rr[6];  down_rr[6]<=down;down_r[6]<=down_rr[6];end
         'b0111:begin up_rr[7]<= up;up_r[7]<= up_rr[7];  down_rr[7]<=down;down_r[7]<=down_rr[7];end
         'b1000:begin up_rr[8]<= up;up_r[8]<= up_rr[8];  down_rr[8]<=down;down_r[8]<=down_rr[8];end
         'b1001:begin up_rr[9]<= up;up_r[9]<= up_rr[9];  down_rr[9]<=down;down_r[9]<=down_rr[9];end
         'b1010:begin up_rr[10]<= up;up_r[10]<= up_rr[10];  down_rr[10]<=down;down_r[10]<=down_rr[10];end
         'b1011:begin up_rr[11]<= up;up_r[11]<= up_rr[11];  down_rr[11]<=down;down_r[11]<=down_rr[11];end
         'b1100:begin up_rr[12]<= up;up_r[12]<= up_rr[12];  down_rr[12]<=down;down_r[12]<=down_rr[12];end
         'b1101:begin up_rr[13]<= up;up_r[13]<= up_rr[13];  down_rr[13]<=down;down_r[13]<=down_rr[13];end
         'b1110:begin up_rr[14]<= up;up_r[14]<= up_rr[14];  down_rr[14]<=down;down_r[14]<=down_rr[14];end
         'b1111:begin up_rr[15]<= up;up_r[15]<= up_rr[15];  down_rr[15]<=down;down_r[15]<=down_rr[15];end
			 
      endcase

     end
end   
endmodule