play.map.rpt

通过VERILOG HDL语言使用CPLD连接PS2键盘.

; alt_mercury_add_sub.inc          ; yes             ; Other                  ; c:/altera/quartus50/libraries/megafunctions/alt_mercury_add_sub.inc ;
; aglobal50.inc                    ; yes             ; Other                  ; c:/altera/quartus50/libraries/megafunctions/aglobal50.inc           ;
; addcore.tdf                      ; yes             ; Megafunction           ; c:/altera/quartus50/libraries/megafunctions/addcore.tdf             ;
; a_csnbuffer.inc                  ; yes             ; Other                  ; c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.inc         ;
; a_csnbuffer.tdf                  ; yes             ; Megafunction           ; c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf         ;
; look_add.tdf                     ; yes             ; Megafunction           ; c:/altera/quartus50/libraries/megafunctions/look_add.tdf            ;
; altshift.tdf                     ; yes             ; Megafunction           ; c:/altera/quartus50/libraries/megafunctions/altshift.tdf            ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 25                   ;
; Total registers      ; 25                   ;
; I/O pins             ; 2                    ;
; Shareable expanders  ; 1                    ;
; Maximum fan-out node ; counter4Hz[0]        ;
; Maximum fan-out      ; 26                   ;
; Total fan-out        ; 511                  ;
; Average fan-out      ; 18.25                ;
+----------------------+----------------------+


+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                  ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |play                      ; 25         ; 2    ; |play               ;
+----------------------------+------------+------+---------------------+


+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_0 ;
+------------------------+-------------+---------------------------------+
; Parameter Name         ; Value       ; Type                            ;
+------------------------+-------------+---------------------------------+
; LPM_WIDTH              ; 24          ; Untyped                         ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                         ;
; LPM_DIRECTION          ; ADD         ; Untyped                         ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                         ;
; LPM_PIPELINE           ; 0           ; Untyped                         ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                         ;
; REGISTERED_AT_END      ; 0           ; Untyped                         ;
; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                         ;
; USE_CS_BUFFERS         ; 1           ; Untyped                         ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                         ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH              ;
; DEVICE_FAMILY          ; MAX3000A    ; Untyped                         ;
; USE_WYS                ; OFF         ; Untyped                         ;
; STYLE                  ; FAST        ; Untyped                         ;
; CBXI_PARAMETER         ; add_sub_joh ; Untyped                         ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                  ;
+------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/altera/quartus50/speak/play.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Fri Jul 06 00:18:33 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off play -c play
Info: Found 1 design units, including 1 entities, in source file play.v
    Info: Found entity 1: play
Info: Elaborating entity "play" for the top level hierarchy
Warning: Verilog HDL assignment warning at play.v(10): truncated value with size 32 to match size of target (24)
Warning: Verilog HDL assignment warning at play.v(15): truncated value with size 32 to match size of target (24)
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 24 buffer(s)
    Info: Ignored 24 SOFT buffer(s)
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "sys_CLK" to global clock signal
Info: Implemented 28 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 1 output pins
    Info: Implemented 25 macrocells
    Info: Implemented 1 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Fri Jul 06 00:18:38 2007
    Info: Elapsed time: 00:00:06