liushui.v

通过VERILOG HDL语言使用CPLD连接PS2键盘.

module liushui(clk,led,reset);
input clk;
input reset;
output[7:0] led;
reg[26:0] count;
reg[7:0] ledd;
always@ (posedge clk)
begin
if(reset==1)
begin
count=count+1;
end
else
count=0;
end
always@ (count[26:24])
begin
case (count[26:24])
3'b000:ledd=8'b00000001;
3'b001:ledd=8'b00000010;
3'b010:ledd=8'b00000100;
3'b011:ledd=8'b00001000;
3'b100:ledd=8'b00010000;
3'b101:ledd=8'b00100000;
3'b110:ledd=8'b01000000;
3'b111:ledd=8'b10000000;
endcase
end
assign led=ledd;
endmodule