liushui.tan.summary

通过VERILOG HDL语言使用CPLD连接PS2键盘.

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.700 ns
From           : reset
To             : lpm_counter:count_rtl_0|dffs[26]
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.700 ns
From           : lpm_counter:count_rtl_0|dffs[26]
To             : led[2]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.500 ns
From           : reset
To             : lpm_counter:count_rtl_0|dffs[26]
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 97.09 MHz ( period = 10.300 ns )
From           : lpm_counter:count_rtl_0|dffs[9]
To             : lpm_counter:count_rtl_0|dffs[20]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------