📄 adc.map.rpt
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Analysis & Synthesis report for adc
Thu Jul 05 23:21:17 2007
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. State Machine - |adc|state1
8. User-Specified and Inferred Latches
9. Parameter Settings for User Entity Instance: Top-level Entity: |adc
10. Parameter Settings for Inferred Entity Instance: lpm_counter:count1_rtl_0
11. Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_1
12. Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_2
13. Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_3
14. Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_4
15. Analysis & Synthesis Equations
16. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Jul 05 23:21:17 2007 ;
; Quartus II Version ; 5.0 Build 168 06/22/2005 SP 1 SJ Full Version ;
; Revision Name ; adc ;
; Top-level Entity Name ; adc ;
; Family ; MAX3000A ;
; Total macrocells ; 88 ;
; Total pins ; 24 ;
+-----------------------------+-----------------------------------------------+
+---------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------+------------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------+------------------+---------------+
; Device ; EPM3128ATC100-10 ; ;
; Top-level entity name ; adc ; adc ;
; Family name ; MAX3000A ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; off ; off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Auto ; Auto ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A ; Speed ; Speed ;
; Allow XOR Gate Usage ; On ; On ;
; Auto Logic Cell Insertion ; On ; On ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4 ; 4 ;
; Auto Parallel Expanders ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A ; 100 ; 100 ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+----------------------------------------------------------------------+------------------+---------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------+
; adc.v ; yes ; User Verilog HDL File ; C:/altera/quartus50/ADC0804/adc.v ;
; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf ;
; lpm_constant.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/lpm_constant.inc ;
; lpm_decode.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/lpm_decode.inc ;
; lpm_add_sub.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.inc ;
; cmpconst.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/cmpconst.inc ;
; lpm_compare.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/lpm_compare.inc ;
; lpm_counter.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/lpm_counter.inc ;
; dffeea.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/dffeea.inc ;
; alt_synch_counter.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/alt_synch_counter.inc ;
; alt_synch_counter_f.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.inc ;
; alt_counter_stratix.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal50.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/aglobal50.inc ;
; lpm_add_sub.tdf ; yes ; Megafunction ; c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf ;
; addcore.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/addcore.inc ;
; look_add.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/look_add.inc ;
; bypassff.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/bypassff.inc ;
; altshift.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/altshift.inc ;
; alt_stratix_add_sub.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/alt_stratix_add_sub.inc ;
; alt_mercury_add_sub.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/alt_mercury_add_sub.inc ;
; addcore.tdf ; yes ; Megafunction ; c:/altera/quartus50/libraries/megafunctions/addcore.tdf ;
; a_csnbuffer.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.inc ;
; a_csnbuffer.tdf ; yes ; Megafunction ; c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf ;
; look_add.tdf ; yes ; Megafunction ; c:/altera/quartus50/libraries/megafunctions/look_add.tdf ;
; altshift.tdf ; yes ; Megafunction ; c:/altera/quartus50/libraries/megafunctions/altshift.tdf ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 88 ;
; Total registers ; 41 ;
; I/O pins ; 24 ;
; Shareable expanders ; 16 ;
; Parallel expanders ; 14 ;
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