adc.map.qmsg

通过VERILOG HDL语言使用CPLD连接PS2键盘.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 05 23:21:05 2007 " "Info: Processing started: Thu Jul 05 23:21:05 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adc -c adc " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adc -c adc" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adc.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file adc.v" { { "Info" "ISGN_ENTITY_NAME" "1 adc " "Info: Found entity 1: adc" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "adc " "Info: Elaborating entity \"adc\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 adc.v(35) " "Warning: Verilog HDL assignment warning at adc.v(35): truncated value with size 32 to match size of target (1)" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 35 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 adc.v(39) " "Warning: Verilog HDL assignment warning at adc.v(39): truncated value with size 32 to match size of target (12)" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 39 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 adc.v(40) " "Warning: Verilog HDL assignment warning at adc.v(40): truncated value with size 32 to match size of target (1)" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 40 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 adc.v(45) " "Warning: Verilog HDL assignment warning at adc.v(45): truncated value with size 32 to match size of target (5)" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 45 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 adc.v(49) " "Warning: Verilog HDL assignment warning at adc.v(49): truncated value with size 32 to match size of target (1)" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 49 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 adc.v(52) " "Warning: Verilog HDL assignment warning at adc.v(52): truncated value with size 32 to match size of target (1)" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 52 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "nop1 adc.v(62) " "Warning: Verilog HDL Always Construct warning at adc.v(62): variable \"nop1\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 62 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "nop1 adc.v(84) " "Warning: Verilog HDL Always Construct warning at adc.v(84): variable \"nop1\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 84 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 adc.v(111) " "Warning: Verilog HDL assignment warning at adc.v(111): truncated value with size 32 to match size of target (12)" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 111 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 adc.v(115) " "Warning: Verilog HDL assignment warning at adc.v(115): truncated value with size 32 to match size of target (4)" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 115 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 adc.v(120) " "Warning: Verilog HDL assignment warning at adc.v(120): truncated value with size 32 to match size of target (4)" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 120 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 adc.v(134) " "Warning: Verilog HDL assignment warning at adc.v(134): truncated value with size 32 to match size of target (3)" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 134 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "count adc.v(135) " "Warning: Verilog HDL Always Construct warning at adc.v(135): variable \"count\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 135 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 adc.v(139) " "Warning: Verilog HDL assignment warning at adc.v(139): truncated value with size 32 to match size of target (3)" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "count adc.v(140) " "Warning: Verilog HDL Always Construct warning at adc.v(140): variable \"count\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 140 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 adc.v(144) " "Warning: Verilog HDL assignment warning at adc.v(144): truncated value with size 32 to match size of target (3)" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 144 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "count adc.v(145) " "Warning: Verilog HDL Always Construct warning at adc.v(145): variable \"count\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 145 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "adc.v(131) " "Warning: (10270) Verilog HDL statement warning at adc.v(131): incomplete Case Statement has no default case item" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 131 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "weixuann adc.v(129) " "Warning: Verilog HDL Always Construct warning at adc.v(129): variable \"weixuann\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"weixuann\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 129 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "shuma adc.v(129) " "Warning: Verilog HDL Always Construct warning at adc.v(129): variable \"shuma\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"shuma\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 129 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "adc.v(151) " "Warning: (10270) Verilog HDL statement warning at adc.v(151): incomplete Case Statement has no default case item" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 151 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "lddat_reg adc.v(149) " "Warning: Verilog HDL Always Construct warning at adc.v(149): variable \"lddat_reg\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"lddat_reg\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 149 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "count1\[0\]~10 5 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: \"count1\[0\]~10\"" {  } { { "adc.v" "count1\[0\]~10" { Text "C:/altera/quartus50/ADC0804/adc.v" 17 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "look_add.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|adc\|state1 4 0 " "Info: State machine \"\|adc\|state1\" contains 4 states and 0 state bits" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 22 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|adc\|state1 " "Info: Selected Auto state machine encoding method for state machine \"\|adc\|state1\"" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 22 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|adc\|state1 " "Info: Encoding result for state machine \"\|adc\|state1\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "2 " "Info: Completed encoding using 2 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state1~8 " "Info: Encoded state bit \"state1~8\"" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 22 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state1~7 " "Info: Encoded state bit \"state1~7\"" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 22 -1 0 } }  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adc\|state1.st0 00 " "Info: State \"\|adc\|state1.st0\" uses code string \"00\"" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 22 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adc\|state1.st2 10 " "Info: State \"\|adc\|state1.st2\" uses code string \"10\"" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 22 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adc\|state1.st1 01 " "Info: State \"\|adc\|state1.st1\" uses code string \"01\"" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 22 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adc\|state1.st3 11 " "Info: State \"\|adc\|state1.st3\" uses code string \"11\"" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 22 -1 0 } }  } 0}  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 22 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "24 " "Info: Ignored 24 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "24 " "Info: Ignored 24 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "lddat\[7\] VCC " "Warning: Pin \"lddat\[7\]\" stuck at VCC" {  } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "128 " "Info: Implemented 128 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "14 " "Info: Implemented 14 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "88 " "Info: Implemented 88 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "16 " "Info: Implemented 16 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 24 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 24 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 05 23:21:16 2007 " "Info: Processing ended: Thu Jul 05 23:21:16 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0}  } {  } 0}