jianpan1.map.qmsg

通过VERILOG HDL语言使用CPLD连接PS2键盘.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 05 23:52:32 2007 " "Info: Processing started: Thu Jul 05 23:52:32 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off jianpan1 -c jianpan1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jianpan1 -c jianpan1" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jianpan1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file jianpan1.v" { { "Info" "ISGN_ENTITY_NAME" "1 jianpan1 " "Info: Found entity 1: jianpan1" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "jianpan1 " "Info: Elaborating entity \"jianpan1\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "count jianpan1.v(17) " "Warning: Verilog HDL Always Construct warning at jianpan1.v(17): variable \"count\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 17 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "jianpan1.v(17) " "Warning: (10270) Verilog HDL statement warning at jianpan1.v(17): incomplete Case Statement has no default case item" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 17 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "bb jianpan1.v(15) " "Warning: Verilog HDL Always Construct warning at jianpan1.v(15): variable \"bb\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"bb\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 15 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 28 jianpan1.v(28) " "Warning: Verilog HDL assignment warning at jianpan1.v(28): truncated value with size 32 to match size of target (28)" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 28 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 28 jianpan1.v(33) " "Warning: Verilog HDL assignment warning at jianpan1.v(33): truncated value with size 32 to match size of target (28)" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 33 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "a jianpan1.v(40) " "Warning: Verilog HDL Always Construct warning at jianpan1.v(40): variable \"a\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 40 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "bb jianpan1.v(41) " "Warning: Verilog HDL Always Construct warning at jianpan1.v(41): variable \"bb\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 41 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "jianpan1.v(43) " "Warning: (10270) Verilog HDL statement warning at jianpan1.v(43): incomplete Case Statement has no default case item" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 43 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "bb jianpan1.v(57) " "Warning: Verilog HDL Always Construct warning at jianpan1.v(57): variable \"bb\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 57 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "jianpan1.v(59) " "Warning: (10270) Verilog HDL statement warning at jianpan1.v(59): incomplete Case Statement has no default case item" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 59 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "bb jianpan1.v(67) " "Warning: Verilog HDL Always Construct warning at jianpan1.v(67): variable \"bb\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 67 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "jianpan1.v(69) " "Warning: (10270) Verilog HDL statement warning at jianpan1.v(69): incomplete Case Statement has no default case item" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 69 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "bb jianpan1.v(78) " "Warning: Verilog HDL Always Construct warning at jianpan1.v(78): variable \"bb\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 78 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "jianpan1.v(80) " "Warning: (10270) Verilog HDL statement warning at jianpan1.v(80): incomplete Case Statement has no default case item" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 80 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "ledd jianpan1.v(38) " "Warning: Verilog HDL Always Construct warning at jianpan1.v(38): variable \"ledd\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"ledd\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 38 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "ledd jianpan1.v(91) " "Warning: Verilog HDL Always Construct warning at jianpan1.v(91): variable \"ledd\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 91 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "count\[0\]~28 28 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=28) from the following logic: \"count\[0\]~28\"" {  } { { "jianpan1.v" "count\[0\]~28" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 11 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "lddat\[7\] VCC " "Warning: Pin \"lddat\[7\]\" stuck at VCC" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 6 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "wei\[0\] VCC " "Warning: Pin \"wei\[0\]\" stuck at VCC" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 3 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "wei\[1\] GND " "Warning: Pin \"wei\[1\]\" stuck at GND" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 3 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "wei\[2\] GND " "Warning: Pin \"wei\[2\]\" stuck at GND" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 3 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "wei\[3\] GND " "Warning: Pin \"wei\[3\]\" stuck at GND" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 3 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "wei\[4\] GND " "Warning: Pin \"wei\[4\]\" stuck at GND" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 3 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "wei\[5\] GND " "Warning: Pin \"wei\[5\]\" stuck at GND" {  } { { "jianpan1.v" "" { Text "C:/altera/quartus50/keyarray/jianpan1.v" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "91 " "Info: Implemented 91 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "18 " "Info: Implemented 18 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "68 " "Info: Implemented 68 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 24 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 24 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 05 23:52:36 2007 " "Info: Processing ended: Thu Jul 05 23:52:36 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}