jianpan1.v

通过VERILOG HDL语言使用CPLD连接PS2键盘.

module jianpan1 (clk,a,b,lddat,wei);
input clk;
output [5:0] wei;
input  [3:0] a;
output [3:0] b;
output [7:0]lddat;
reg [7:0] lddat_reg;
reg  [3:0] aa;
reg [3:0] bb;
reg [3:0] ledd;
reg [27:0] count;
reg scanclk;


always @ (scanclk)
begin
case(count[24:22])
3'b000:bb=4'b1110;
3'b010:bb=4'b1101;
3'b100:bb=4'b1011;
3'b110:bb=4'b0111;
endcase
end
always @ (posedge clk)
begin
if (count==28'hfffffff)
begin
count=0;
scanclk=~scanclk;
end
else
begin
count=count+1;
//bb=4'b1101;
end
end
assign b=bb;
always @ (count[5])
begin
aa=a;
if(bb==4'b1101)
begin
case(aa)
4'b0111:ledd=4'b1011;//11
4'b1011:ledd=4'b1010;//10
4'b1101:ledd=4'b1001;//9
4'b1110:ledd=4'b1000;//8

//default ledd=4'b1111;
//else if(aa==4'b1101)
//ledd=4'b0010;
//else if(aa==4'b1110)
//ledd=4'b0001;                                                                                                
//else ledd=4'b0000;
endcase
end
else if(bb==4'b1110)
begin
case(aa)
4'b0111:ledd=4'b1111;//15
4'b1011:ledd=4'b1110;//14
4'b1101:ledd=4'b1101;//13
4'b1110:ledd=4'b1100;//12
//default ledd=4'b1111;
endcase
end
else if(bb==4'b0111)
begin
case(aa)
4'b0111:ledd=4'b0011;//3
4'b1011:ledd=4'b0010;//2
4'b1101:ledd=4'b0001;//1
4'b1110:ledd=4'b0000;//0

//default ledd=4'b1111;
endcase
end
else if(bb==4'b1011)
begin
case(aa)
4'b0111:ledd=4'b0111;//7
4'b1011:ledd=4'b0110;//6
4'b1101:ledd=4'b0101;//5
4'b1110:ledd=4'b0100;//4
//default ledd=4'b1111;
endcase
end
end
always @ (clk)
begin 
case(ledd)
4'h0: lddat_reg = 8'hc0;
4'h1: lddat_reg = 8'hf9;		
4'h2: lddat_reg = 8'ha4;				
4'h3: lddat_reg = 8'hb0;
4'h4: lddat_reg = 8'h99;	
4'h5: lddat_reg = 8'h92;	
4'h6: lddat_reg = 8'h82;
4'h7: lddat_reg = 8'hf8;		
4'h8: lddat_reg = 8'h80;				
4'h9: lddat_reg = 8'h90;
4'ha: lddat_reg = 8'h88;
4'hb: lddat_reg = 8'h83;	
4'hc: lddat_reg = 8'hc6;
4'hd: lddat_reg = 8'ha1;
4'he: lddat_reg = 8'h86;	
4'hf: lddat_reg = 8'h8e;	
//default lddat_reg=8'h00;	
endcase
end		
assign  lddat=lddat_reg;
//assign kongzhi=1;
assign wei=6'b000001;
endmodule