jishu2.map.qmsg

通过VERILOG HDL语言使用CPLD连接PS2键盘.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 05 22:49:29 2007 " "Info: Processing started: Thu Jul 05 22:49:29 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off jishu2 -c jishu2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jishu2 -c jishu2" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jishu2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file jishu2.v" { { "Info" "ISGN_ENTITY_NAME" "1 jishu2 " "Info: Found entity 1: jishu2" {  } { { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "jishu2 " "Info: Elaborating entity \"jishu2\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 jishu2.v(15) " "Warning: Verilog HDL assignment warning at jishu2.v(15): truncated value with size 32 to match size of target (4)" {  } { { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 15 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "jishu2.v(36) " "Warning: (10270) Verilog HDL statement warning at jishu2.v(36): incomplete Case Statement has no default case item" {  } { { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 36 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "duanreg jishu2.v(34) " "Warning: Verilog HDL Always Construct warning at jishu2.v(34): variable \"duanreg\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"duanreg\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 34 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "look_add.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "32 " "Info: Ignored 32 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "32 " "Info: Ignored 32 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "duan\[7\] VCC " "Warning: Pin \"duan\[7\]\" stuck at VCC" {  } { { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 3 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "wei\[2\] GND " "Warning: Pin \"wei\[2\]\" stuck at GND" {  } { { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 4 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "wei\[3\] GND " "Warning: Pin \"wei\[3\]\" stuck at GND" {  } { { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 4 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "wei\[4\] GND " "Warning: Pin \"wei\[4\]\" stuck at GND" {  } { { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 4 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "wei\[5\] GND " "Warning: Pin \"wei\[5\]\" stuck at GND" {  } { { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "92 " "Info: Implemented 92 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "14 " "Info: Implemented 14 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "66 " "Info: Implemented 66 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "11 " "Info: Implemented 11 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 05 22:49:39 2007 " "Info: Processing ended: Thu Jul 05 22:49:39 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0}  } {  } 0}