ps2.tan.qmsg

通过VERILOG HDL语言使用CPLD连接PS2键盘.

{ "Info" "ITDB_TH_RESULT" "save_scan_code\[1\] key_data sys_clock 4.000 ns register " "Info: th for register \"save_scan_code\[1\]\" (data pin = \"key_data\", clock pin = \"sys_clock\") is 4.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clock destination 9.800 ns + Longest register " "Info: + Longest clock path from clock \"sys_clock\" to destination register is 9.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns sys_clock 1 CLK PIN_87 15 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 15; CLK Node = 'sys_clock'" {  } { { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "" { sys_clock } "NODE_NAME" } "" } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns smooth_key_clock 2 REG LC11 17 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC11; Fanout = 17; REG Node = 'smooth_key_clock'" {  } { { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "2.500 ns" { sys_clock smooth_key_clock } "NODE_NAME" } "" } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(2.200 ns) 9.800 ns save_scan_code\[1\] 3 REG LC10 4 " "Info: 3: + IC(2.600 ns) + CELL(2.200 ns) = 9.800 ns; Loc. = LC10; Fanout = 4; REG Node = 'save_scan_code\[1\]'" {  } { { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "4.800 ns" { smooth_key_clock save_scan_code[1] } "NODE_NAME" } "" } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns 73.47 % " "Info: Total cell delay = 7.200 ns ( 73.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns 26.53 % " "Info: Total interconnect delay = 2.600 ns ( 26.53 % )" {  } {  } 0}  } { { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "9.800 ns" { sys_clock smooth_key_clock save_scan_code[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.800 ns" { sys_clock sys_clock~out smooth_key_clock save_scan_code[1] } { 0.000ns 0.000ns 0.000ns 2.600ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.100 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns key_data 1 PIN PIN_67 18 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_67; Fanout = 18; PIN Node = 'key_data'" {  } { { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "" { key_data } "NODE_NAME" } "" } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(3.100 ns) 7.100 ns save_scan_code\[1\] 2 REG LC10 4 " "Info: 2: + IC(2.600 ns) + CELL(3.100 ns) = 7.100 ns; Loc. = LC10; Fanout = 4; REG Node = 'save_scan_code\[1\]'" {  } { { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "5.700 ns" { key_data save_scan_code[1] } "NODE_NAME" } "" } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns 63.38 % " "Info: Total cell delay = 4.500 ns ( 63.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns 36.62 % " "Info: Total interconnect delay = 2.600 ns ( 36.62 % )" {  } {  } 0}  } { { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "7.100 ns" { key_data save_scan_code[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.100 ns" { key_data key_data~out save_scan_code[1] } { 0.000ns 0.000ns 2.600ns } { 0.000ns 1.400ns 3.100ns } } }  } 0}  } { { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "9.800 ns" { sys_clock smooth_key_clock save_scan_code[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.800 ns" { sys_clock sys_clock~out smooth_key_clock save_scan_code[1] } { 0.000ns 0.000ns 0.000ns 2.600ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "7.100 ns" { key_data save_scan_code[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.100 ns" { key_data key_data~out save_scan_code[1] } { 0.000ns 0.000ns 2.600ns } { 0.000ns 1.400ns 3.100ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 06 00:07:23 2007 " "Info: Processing ended: Fri Jul 06 00:07:23 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}