ps2.tan.qmsg

通过VERILOG HDL语言使用CPLD连接PS2键盘.

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "sys_clock " "Info: Assuming node \"sys_clock\" is an undefined clock" {  } { { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 7 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sys_clock" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "scan_end~reg0 " "Info: Detected ripple clock \"scan_end~reg0\" as buffer" {  } { { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 51 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "scan_end~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "smooth_key_clock " "Info: Detected ripple clock \"smooth_key_clock\" as buffer" {  } { { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 18 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "smooth_key_clock" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sys_clock register save_scan_code\[6\] register save_scan_code\[6\] 97.09 MHz 10.3 ns Internal " "Info: Clock \"sys_clock\" has Internal fmax of 97.09 MHz between source register \"save_scan_code\[6\]\" and destination register \"save_scan_code\[6\]\" (period= 10.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.800 ns + Longest register register " "Info: + Longest register to register delay is 5.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns save_scan_code\[6\] 1 REG LC2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 4; REG Node = 'save_scan_code\[6\]'" {  } { { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "" { save_scan_code[6] } "NODE_NAME" } "" } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.100 ns) 5.800 ns save_scan_code\[6\] 2 REG LC2 4 " "Info: 2: + IC(2.700 ns) + CELL(3.100 ns) = 5.800 ns; Loc. = LC2; Fanout = 4; REG Node = 'save_scan_code\[6\]'" {  } { { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "5.800 ns" { save_scan_code[6] save_scan_code[6] } "NODE_NAME" } "" } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.100 ns 53.45 % " "Info: Total cell delay = 3.100 ns ( 53.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns 46.55 % " "Info: Total interconnect delay = 2.700 ns ( 46.55 % )" {  } {  } 0}  } { { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "5.800 ns" { save_scan_code[6] save_scan_code[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.800 ns" { save_scan_code[6] save_scan_code[6] } { 0.000ns 2.700ns } { 0.000ns 3.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clock destination 9.800 ns + Shortest register " "Info: + Shortest clock path from clock \"sys_clock\" to destination register is 9.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns sys_clock 1 CLK PIN_87 15 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 15; CLK Node = 'sys_clock'" {  } { { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "" { sys_clock } "NODE_NAME" } "" } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns smooth_key_clock 2 REG LC11 17 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC11; Fanout = 17; REG Node = 'smooth_key_clock'" {  } { { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "2.500 ns" { sys_clock smooth_key_clock } "NODE_NAME" } "" } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(2.200 ns) 9.800 ns save_scan_code\[6\] 3 REG LC2 4 " "Info: 3: + IC(2.600 ns) + CELL(2.200 ns) = 9.800 ns; Loc. = LC2; Fanout = 4; REG Node = 'save_scan_code\[6\]'" {  } { { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "4.800 ns" { smooth_key_clock save_scan_code[6] } "NODE_NAME" } "" } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns 73.47 % " "Info: Total cell delay = 7.200 ns ( 73.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns 26.53 % " "Info: Total interconnect delay = 2.600 ns ( 26.53 % )" {  } {  } 0}  } { { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "9.800 ns" { sys_clock smooth_key_clock save_scan_code[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.800 ns" { sys_clock sys_clock~out smooth_key_clock save_scan_code[6] } { 0.000ns 0.000ns 0.000ns 2.600ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clock source 9.800 ns - Longest register " "Info: - Longest clock path from clock \"sys_clock\" to source register is 9.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns sys_clock 1 CLK PIN_87 15 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 15; CLK Node = 'sys_clock'" {  } { { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "" { sys_clock } "NODE_NAME" } "" } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns smooth_key_clock 2 REG LC11 17 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC11; Fanout = 17; REG Node = 'smooth_key_clock'" {  } { { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "2.500 ns" { sys_clock smooth_key_clock } "NODE_NAME" } "" } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(2.200 ns) 9.800 ns save_scan_code\[6\] 3 REG LC2 4 " "Info: 3: + IC(2.600 ns) + CELL(2.200 ns) = 9.800 ns; Loc. = LC2; Fanout = 4; REG Node = 'save_scan_code\[6\]'" {  } { { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "4.800 ns" { smooth_key_clock save_scan_code[6] } "NODE_NAME" } "" } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns 73.47 % " "Info: Total cell delay = 7.200 ns ( 73.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns 26.53 % " "Info: Total interconnect delay = 2.600 ns ( 26.53 % )" {  } {  } 0}  } { { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "9.800 ns" { sys_clock smooth_key_clock save_scan_code[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.800 ns" { sys_clock sys_clock~out smooth_key_clock save_scan_code[6] } { 0.000ns 0.000ns 0.000ns 2.600ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0}  } { { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "9.800 ns" { sys_clock smooth_key_clock save_scan_code[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.800 ns" { sys_clock sys_clock~out smooth_key_clock save_scan_code[6] } { 0.000ns 0.000ns 0.000ns 2.600ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "9.800 ns" { sys_clock smooth_key_clock save_scan_code[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.800 ns" { sys_clock sys_clock~out smooth_key_clock save_scan_code[6] } { 0.000ns 0.000ns 0.000ns 2.600ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 19 -1 0 } }  } 0}  } { { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "5.800 ns" { save_scan_code[6] save_scan_code[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.800 ns" { save_scan_code[6] save_scan_code[6] } { 0.000ns 2.700ns } { 0.000ns 3.100ns } } } { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "9.800 ns" { sys_clock smooth_key_clock save_scan_code[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.800 ns" { sys_clock sys_clock~out smooth_key_clock save_scan_code[6] } { 0.000ns 0.000ns 0.000ns 2.600ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2LEDdisplay/db/ps2_cmp.qrpt" Compiler "ps2" "UNKNOWN" "V1" "C:/altera/quartus50/PS2LEDdisplay/db/ps2.quartus_db" { Floorplan "C:/altera/quartus50/PS2LEDdisplay/" "" "9.800 ns" { sys_clock smooth_key_clock save_scan_code[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.800 ns" { sys_clock sys_clock~out smooth_key_clock save_scan_code[6] } { 0.000ns 0.000ns 0.000ns 2.600ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0}