ps2.map.qmsg

通过VERILOG HDL语言使用CPLD连接PS2键盘.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jul 06 00:07:10 2007 " "Info: Processing started: Fri Jul 06 00:07:10 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ps2 -c ps2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ps2 -c ps2" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ps2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ps2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ps2-rtl " "Info: Found design unit 1: ps2-rtl" {  } { { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ps2 " "Info: Found entity 1: ps2" {  } { { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ps2 " "Info: Elaborating entity \"ps2\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 18 -1 0 } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 17 -1 0 } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 17 -1 0 } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 17 -1 0 } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 17 -1 0 } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 17 -1 0 } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 17 -1 0 } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 17 -1 0 } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 17 -1 0 } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 17 -1 0 } } { "ps2.vhd" "" { Text "C:/altera/quartus50/PS2LEDdisplay/ps2.vhd" 17 -1 0 } }  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "sys_clock " "Info: Promoted clock signal driven by pin \"sys_clock\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "52 " "Info: Implemented 52 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "38 " "Info: Implemented 38 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 06 00:07:14 2007 " "Info: Processing ended: Fri Jul 06 00:07:14 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}