ps2.tan.summary

通过VERILOG HDL语言使用CPLD连接PS2键盘.

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.600 ns
From           : key_clock
To             : filter[2]
From Clock     : 
To Clock       : sys_clock
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 19.600 ns
From           : scan_code[0]~reg0
To             : scan_code[0]
From Clock     : sys_clock
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 4.000 ns
From           : key_data
To             : save_scan_code[6]
From Clock     : 
To Clock       : sys_clock
Failed Paths   : 0

Type           : Clock Setup: 'sys_clock'
Slack          : N/A
Required Time  : None
Actual Time    : 97.09 MHz ( period = 10.300 ns )
From           : save_scan_code[1]
To             : save_scan_code[1]
From Clock     : sys_clock
To Clock       : sys_clock
Failed Paths   : 0

Type           : Clock Hold: 'sys_clock'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : save_scan_code[9]
To             : scan_parity~reg0
From Clock     : sys_clock
To Clock       : sys_clock
Failed Paths   : 9

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 9

--------------------------------------------------------------------------------------