dianzhen1.tan.qmsg

通过VERILOG HDL语言使用CPLD连接PS2键盘.

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "dianzhen1.v" "" { Text "C:/altera/quartus50/88led_array/dianzhen1.v" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register lpm_counter:count_rtl_0\|dffs\[0\] register lpm_counter:count_rtl_0\|dffs\[25\] 96.15 MHz 10.4 ns Internal " "Info: Clock \"clock\" has Internal fmax of 96.15 MHz between source register \"lpm_counter:count_rtl_0\|dffs\[0\]\" and destination register \"lpm_counter:count_rtl_0\|dffs\[25\]\" (period= 10.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.900 ns + Longest register register " "Info: + Longest register to register delay is 5.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:count_rtl_0\|dffs\[0\] 1 REG LC49 26 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC49; Fanout = 26; REG Node = 'lpm_counter:count_rtl_0\|dffs\[0\]'" {  } { { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "" { lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(3.100 ns) 5.900 ns lpm_counter:count_rtl_0\|dffs\[25\] 2 REG LC23 31 " "Info: 2: + IC(2.800 ns) + CELL(3.100 ns) = 5.900 ns; Loc. = LC23; Fanout = 31; REG Node = 'lpm_counter:count_rtl_0\|dffs\[25\]'" {  } { { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "5.900 ns" { lpm_counter:count_rtl_0|dffs[0] lpm_counter:count_rtl_0|dffs[25] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.100 ns 52.54 % " "Info: Total cell delay = 3.100 ns ( 52.54 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns 47.46 % " "Info: Total interconnect delay = 2.800 ns ( 47.46 % )" {  } {  } 0}  } { { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "5.900 ns" { lpm_counter:count_rtl_0|dffs[0] lpm_counter:count_rtl_0|dffs[25] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.900 ns" { lpm_counter:count_rtl_0|dffs[0] lpm_counter:count_rtl_0|dffs[25] } { 0.000ns 2.800ns } { 0.000ns 3.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock 1 CLK PIN_87 26 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 26; CLK Node = 'clock'" {  } { { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "" { clock } "NODE_NAME" } "" } } { "dianzhen1.v" "" { Text "C:/altera/quartus50/88led_array/dianzhen1.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns lpm_counter:count_rtl_0\|dffs\[25\] 2 REG LC23 31 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC23; Fanout = 31; REG Node = 'lpm_counter:count_rtl_0\|dffs\[25\]'" {  } { { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "0.900 ns" { clock lpm_counter:count_rtl_0|dffs[25] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "3.400 ns" { clock lpm_counter:count_rtl_0|dffs[25] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[25] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.400 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock 1 CLK PIN_87 26 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 26; CLK Node = 'clock'" {  } { { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "" { clock } "NODE_NAME" } "" } } { "dianzhen1.v" "" { Text "C:/altera/quartus50/88led_array/dianzhen1.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns lpm_counter:count_rtl_0\|dffs\[0\] 2 REG LC49 26 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC49; Fanout = 26; REG Node = 'lpm_counter:count_rtl_0\|dffs\[0\]'" {  } { { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "0.900 ns" { clock lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "3.400 ns" { clock lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0}  } { { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "3.400 ns" { clock lpm_counter:count_rtl_0|dffs[25] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[25] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "3.400 ns" { clock lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0}  } { { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "5.900 ns" { lpm_counter:count_rtl_0|dffs[0] lpm_counter:count_rtl_0|dffs[25] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.900 ns" { lpm_counter:count_rtl_0|dffs[0] lpm_counter:count_rtl_0|dffs[25] } { 0.000ns 2.800ns } { 0.000ns 3.100ns } } } { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "3.400 ns" { clock lpm_counter:count_rtl_0|dffs[25] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[25] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "3.400 ns" { clock lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock ldoa\[5\] lpm_counter:count_rtl_0\|dffs\[10\] 14.700 ns register " "Info: tco from clock \"clock\" to destination pin \"ldoa\[5\]\" through register \"lpm_counter:count_rtl_0\|dffs\[10\]\" is 14.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.400 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock 1 CLK PIN_87 26 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 26; CLK Node = 'clock'" {  } { { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "" { clock } "NODE_NAME" } "" } } { "dianzhen1.v" "" { Text "C:/altera/quartus50/88led_array/dianzhen1.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns lpm_counter:count_rtl_0\|dffs\[10\] 2 REG LC2 57 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC2; Fanout = 57; REG Node = 'lpm_counter:count_rtl_0\|dffs\[10\]'" {  } { { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "0.900 ns" { clock lpm_counter:count_rtl_0|dffs[10] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "3.400 ns" { clock lpm_counter:count_rtl_0|dffs[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[10] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.700 ns + Longest register pin " "Info: + Longest register to pin delay is 9.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:count_rtl_0\|dffs\[10\] 1 REG LC2 57 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 57; REG Node = 'lpm_counter:count_rtl_0\|dffs\[10\]'" {  } { { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "" { lpm_counter:count_rtl_0|dffs[10] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(1.300 ns) 4.100 ns Select~2038 2 COMB LC42 1 " "Info: 2: + IC(2.800 ns) + CELL(1.300 ns) = 4.100 ns; Loc. = LC42; Fanout = 1; COMB Node = 'Select~2038'" {  } { { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "4.100 ns" { lpm_counter:count_rtl_0|dffs[10] Select~2038 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 8.100 ns Select~2027 3 COMB LC43 1 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 8.100 ns; Loc. = LC43; Fanout = 1; COMB Node = 'Select~2027'" {  } { { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "4.000 ns" { Select~2038 Select~2027 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 9.700 ns ldoa\[5\] 4 PIN PIN_19 0 " "Info: 4: + IC(0.000 ns) + CELL(1.600 ns) = 9.700 ns; Loc. = PIN_19; Fanout = 0; PIN Node = 'ldoa\[5\]'" {  } { { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "1.600 ns" { Select~2027 ldoa[5] } "NODE_NAME" } "" } } { "dianzhen1.v" "" { Text "C:/altera/quartus50/88led_array/dianzhen1.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.900 ns 71.13 % " "Info: Total cell delay = 6.900 ns ( 71.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns 28.87 % " "Info: Total interconnect delay = 2.800 ns ( 28.87 % )" {  } {  } 0}  } { { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "9.700 ns" { lpm_counter:count_rtl_0|dffs[10] Select~2038 Select~2027 ldoa[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.700 ns" { lpm_counter:count_rtl_0|dffs[10] Select~2038 Select~2027 ldoa[5] } { 0.000ns 2.800ns 0.000ns 0.000ns } { 0.000ns 1.300ns 4.000ns 1.600ns } } }  } 0}  } { { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "3.400 ns" { clock lpm_counter:count_rtl_0|dffs[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[10] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" "" { Report "C:/altera/quartus50/88led_array/db/dianzhen1_cmp.qrpt" Compiler "dianzhen1" "UNKNOWN" "V1" "C:/altera/quartus50/88led_array/db/dianzhen1.quartus_db" { Floorplan "C:/altera/quartus50/88led_array/" "" "9.700 ns" { lpm_counter:count_rtl_0|dffs[10] Select~2038 Select~2027 ldoa[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.700 ns" { lpm_counter:count_rtl_0|dffs[10] Select~2038 Select~2027 ldoa[5] } { 0.000ns 2.800ns 0.000ns 0.000ns } { 0.000ns 1.300ns 4.000ns 1.600ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 05 23:12:51 2007 " "Info: Processing ended: Thu Jul 05 23:12:51 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}