ps21.map.qmsg

通过VERILOG HDL语言使用CPLD连接PS2键盘.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jul 06 00:11:09 2007 " "Info: Processing started: Fri Jul 06 00:11:09 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ps21 -c ps21 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ps21 -c ps21" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ps21.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ps21.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ps21-rtl " "Info: Found design unit 1: ps21-rtl" {  } { { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 20 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ps21 " "Info: Found entity 1: ps21" {  } { { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ps21 " "Info: Elaborating entity \"ps21\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "save_scan_code ps21.vhd(81) " "Warning: VHDL Process Statement warning at ps21.vhd(81): signal \"save_scan_code\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 81 0 0 } }  } 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 22 -1 0 } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 21 -1 0 } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 21 -1 0 } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 21 -1 0 } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 21 -1 0 } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 21 -1 0 } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 21 -1 0 } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 21 -1 0 } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 21 -1 0 } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 21 -1 0 } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 21 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "wei VCC " "Warning: Pin \"wei\" stuck at VCC" {  } { { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 14 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "sys_clock " "Info: Promoted clock signal driven by pin \"sys_clock\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "60 " "Info: Implemented 60 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "40 " "Info: Implemented 40 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "5 " "Info: Implemented 5 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 06 00:11:13 2007 " "Info: Processing ended: Fri Jul 06 00:11:13 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}