ps21.vhd

通过VERILOG HDL语言使用CPLD连接PS2键盘.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ps21 is
    port(
      
        reset         :in std_logic;
        sys_clock    :in std_logic; 
        key_data     :in std_logic;
        key_clock    :in std_logic;
        scan_code    :out std_logic_vector(7 downto 0);
        scan_parity :out std_logic; 
        wei :out std_logic; 
        scan_end     :buffer std_logic  --输出的停止位，设成buffer是因为在串并转换结束后要用它读出并行扫描码
        
        );
end entity ps21;

architecture rtl of ps21 is
    signal filter : std_logic_vector(9 downto 0);           
    signal smooth_key_clock : std_logic;
    signal save_scan_code :std_logic_vector(10 downto 0);
    signal shuma_reg : std_logic_vector(7 downto 0);  
    signal shuma_regg : std_logic_vector(7 downto 0);   
begin
wei<='1';
--这个process用于平滑key_clock
process(reset,sys_clock)
     --取样计数器，只在这个process中有?
variable counter:integer range 0 to 9 :=0; 
  begin
    if reset='0' then 
       filter<="1111111111"; smooth_key_clock<='1';  
 
--在系统时钟的下降沿取样
--将取样数据送到由counter指定的filter位上
    elsif falling_edge(sys_clock) then  
       filter(counter)<=key_clock;   
       
       if counter=9 then counter:=0;  --循环计数器
       else counter:=counter+1;
       end if;

--通过检查取样数据对key_clock进行平滑
       if filter="1111111111" then smooth_key_clock<='1';  
       elsif filter="0000000000" then smooth_key_clock<='0';   
       end if;      
    end if;       
end process;

--这个process用于串并转换
process(reset,smooth_key_clock)    
--串并转换计数器
    variable counter:integer range 0 to 10 :=0; 
  begin
    if reset='0' then scan_end<='0'; counter:=0;
    
    --通过平滑后的同步时钟下降沿提取扫描码
--将key_data的数据送到由counter指定的save_scan_code位上
    elsif falling_edge(smooth_key_clock) then        
       save_scan_code(counter)<=key_data;

       -- scan_end平时是高电平，循环计数器到10时，认为转换结束，将其拉低。
       if counter=10 then scan_end<='0';counter:=0;
       else scan_end<='1';counter:=counter+1;
       end if;
    end if;
end process;

--这个process用于在串并转换结束后，将扫描码和校验位送出
process(scan_end)
  begin    
    if  falling_edge(scan_end) then 
           scan_code<=shuma_regg;
      scan_parity<=save_scan_code(9);    
    end if;
end process;
process(shuma_reg)
    begin
    shuma_reg <=save_scan_code(8 downto 1);
    case shuma_reg is
      when "01000101"=> 
      shuma_regg<="11000000";
      when "00010110"=> 
      shuma_regg<="11111001";
      when "00011110"=> 
      shuma_regg<="10100100";
      when "00100110"=> 
      shuma_regg<="10110000";
      when "00100101"=> 
      shuma_regg<="10011001";
      when "00101110"=> 
      shuma_regg<="10010010";
      when "00110110"=> 
      shuma_regg<="10000010";
      when "00111101"=> 
      shuma_regg<="11111000";
      when "00111110"=> 
      shuma_regg<="10000000";
      when "01000110"=> 
      shuma_regg<="10010000";
      when others=> shuma_regg<="00000000";
      end case;
end process;   
end architecture rtl;