clock6.map.qmsg

通过VERILOG HDL语言使用CPLD连接PS2键盘.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 05 23:27:55 2007 " "Info: Processing started: Thu Jul 05 23:27:55 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock6 -c clock6 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock6 -c clock6" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock6.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clock6.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock6 " "Info: Found entity 1: clock6" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock6 " "Info: Elaborating entity \"clock6\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 clock6.v(13) " "Warning: Verilog HDL assignment warning at clock6.v(13): truncated value with size 32 to match size of target (23)" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "min clock6.v(23) " "Warning: Verilog HDL Always Construct warning at clock6.v(23): variable \"min\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 23 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "min clock6.v(24) " "Warning: Verilog HDL Always Construct warning at clock6.v(24): variable \"min\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 24 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "min clock6.v(25) " "Warning: Verilog HDL Always Construct warning at clock6.v(25): variable \"min\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 25 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "min clock6.v(26) " "Warning: Verilog HDL Always Construct warning at clock6.v(26): variable \"min\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 26 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "min clock6.v(27) " "Warning: Verilog HDL Always Construct warning at clock6.v(27): variable \"min\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 27 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "min clock6.v(28) " "Warning: Verilog HDL Always Construct warning at clock6.v(28): variable \"min\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 28 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "clock6.v(22) " "Warning: (10270) Verilog HDL statement warning at clock6.v(22): incomplete Case Statement has no default case item" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 22 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "ledbuf clock6.v(20) " "Warning: Verilog HDL Always Construct warning at clock6.v(20): variable \"ledbuf\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"ledbuf\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 20 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "clock6.v(34) " "Warning: (10270) Verilog HDL statement warning at clock6.v(34): incomplete Case Statement has no default case item" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 34 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "lddat_reg clock6.v(32) " "Warning: Verilog HDL Always Construct warning at clock6.v(32): variable \"lddat_reg\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"lddat_reg\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 32 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "clock6.v(50) " "Warning: (10270) Verilog HDL statement warning at clock6.v(50): incomplete Case Statement has no default case item" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 50 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "ldsel_reg clock6.v(48) " "Warning: Verilog HDL Always Construct warning at clock6.v(48): variable \"ldsel_reg\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"ldsel_reg\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 48 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock6.v(62) " "Warning: Verilog HDL assignment warning at clock6.v(62): truncated value with size 32 to match size of target (4)" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 62 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock6.v(66) " "Warning: Verilog HDL assignment warning at clock6.v(66): truncated value with size 32 to match size of target (4)" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 66 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock6.v(70) " "Warning: Verilog HDL assignment warning at clock6.v(70): truncated value with size 32 to match size of target (4)" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 70 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock6.v(74) " "Warning: Verilog HDL assignment warning at clock6.v(74): truncated value with size 32 to match size of target (4)" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 74 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock6.v(78) " "Warning: Verilog HDL assignment warning at clock6.v(78): truncated value with size 32 to match size of target (4)" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 78 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock6.v(82) " "Warning: Verilog HDL assignment warning at clock6.v(82): truncated value with size 32 to match size of target (4)" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 82 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "look_add.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "23 " "Info: Ignored 23 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "23 " "Info: Ignored 23 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "lddat\[7\] VCC " "Warning: Pin \"lddat\[7\]\" stuck at VCC" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "105 " "Info: Implemented 105 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "14 " "Info: Implemented 14 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "79 " "Info: Implemented 79 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "11 " "Info: Implemented 11 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 21 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 21 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 05 23:28:03 2007 " "Info: Processing ended: Thu Jul 05 23:28:03 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0}  } {  } 0}