clock6.fit.eqn

通过VERILOG HDL语言使用CPLD连接PS2键盘.

--min[12] is min[12] at LC51
min[12]_p1_out = min[0] & min[3] & !min[2] & !min[1] & min[4] & min[6] & !min[5] & !min[7] & min[8] & min[11] & !min[10] & !min[9];
min[12]_or_out = min[12]_p1_out;
min[12]_reg_input = min[12]_or_out;
min[12] = TFFE(min[12]_reg_input, !sec, , , );


--min[15] is min[15] at LC55
min[15]_p1_out = min[14] & min[12] & min[13] & min[0] & min[3] & !min[2] & !min[1] & min[4] & min[6] & !min[7] & !min[5] & min[8] & min[11] & !min[10] & !min[9];
min[15]_or_out = min[15]_p1_out;
min[15]_reg_input = min[15]_or_out;
min[15] = TFFE(min[15]_reg_input, !sec, , , );


--min[14] is min[14] at LC31
min[14]_p1_out = !min[15] & min[12] & min[0] & min[3] & !min[2] & !min[1] & min[4] & min[6] & !min[7] & !min[5] & min[8] & min[11] & !min[10] & !min[9] & min[14];
min[14]_p2_out = min[12] & min[0] & min[3] & !min[2] & !min[1] & min[4] & min[6] & !min[7] & !min[5] & min[8] & min[11] & !min[10] & !min[9] & min[13];
min[14]_or_out = min[14]_p1_out # min[14]_p2_out;
min[14]_reg_input = min[14]_or_out;
min[14] = TFFE(min[14]_reg_input, !sec, , , );


--count[9] is count[9] at LC79
count[9]_p1_out = count[8] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[0] & count[1];
count[9]_or_out = count[9];
count[9]_reg_input = count[9]_p1_out $ count[9]_or_out;
count[9] = DFFE(count[9]_reg_input, !GLOBAL(clk), , , );


--min[13] is min[13] at LC28
min[13]_p1_out = !min[14] & min[12] & min[0] & min[3] & !min[2] & !min[1] & min[4] & min[6] & !min[7] & !min[5] & min[8] & min[11] & !min[10] & !min[9];
min[13]_p2_out = min[12] & min[0] & min[3] & !min[2] & !min[1] & min[4] & min[6] & !min[7] & !min[5] & min[8] & min[11] & !min[10] & !min[9] & min[15];
min[13]_p4_out = min[12] & min[0] & min[3] & !min[2] & !min[1] & min[4] & min[6] & !min[7] & !min[5] & min[8] & min[11] & !min[10] & !min[9] & min[13];
min[13]_or_out = min[13]_p1_out # min[13]_p2_out # min[13]_p4_out;
min[13]_reg_input = min[13]_or_out;
min[13] = TFFE(min[13]_reg_input, !sec, , , );


--count[10] is count[10] at LC66
count[10]_p1_out = count[9] & count[8] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[0] & count[1];
count[10]_or_out = count[10];
count[10]_reg_input = count[10]_p1_out $ count[10]_or_out;
count[10] = DFFE(count[10]_reg_input, !GLOBAL(clk), , , );


--min[16] is min[16] at LC26
min[16]_p1_out = min[0] & min[3] & !min[2] & !min[1] & min[4] & min[6] & !min[5] & !min[7] & min[8] & min[11] & !min[10] & !min[9] & min[12] & min[14] & !min[13] & !min[15];
min[16]_or_out = min[16]_p1_out;
min[16]_reg_input = min[16]_or_out;
min[16] = TFFE(min[16]_reg_input, !sec, , , );


--min[19] is min[19] at LC32
min[19]_p1_out = min[18] & min[16] & min[17] & min[0] & min[3] & !min[2] & !min[1] & min[4] & min[6] & !min[7] & !min[5] & min[8] & min[11] & !min[10] & !min[9] & min[12] & min[14] & !min[15] & !min[13];
min[19]_p2_out = !min[18] & min[16] & !min[17] & min[0] & min[3] & !min[2] & !min[1] & min[4] & min[6] & !min[7] & !min[5] & min[8] & min[11] & !min[10] & !min[9] & min[12] & min[14] & !min[15] & !min[13] & min[19];
min[19]_or_out = min[19]_p1_out # min[19]_p2_out;
min[19]_reg_input = min[19]_or_out;
min[19] = TFFE(min[19]_reg_input, !sec, , , );


--count[11] is count[11] at LC65
count[11]_p1_out = count[10] & count[9] & count[8] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[0] & count[1];
count[11]_or_out = count[11];
count[11]_reg_input = count[11]_p1_out $ count[11]_or_out;
count[11] = DFFE(count[11]_reg_input, !GLOBAL(clk), , , );


--min[17] is min[17] at LC27
min[17]_p1_out = !min[19] & min[16] & min[0] & min[3] & !min[2] & !min[1] & min[4] & min[6] & !min[7] & !min[5] & min[8] & min[11] & !min[10] & !min[9] & min[12] & min[14] & !min[15] & !min[13];
min[17]_p2_out = min[16] & min[0] & min[3] & !min[2] & !min[1] & min[4] & min[6] & !min[7] & !min[5] & min[8] & min[11] & !min[10] & !min[9] & min[12] & min[14] & !min[15] & !min[13] & min[18];
min[17]_p4_out = min[16] & min[0] & min[3] & !min[2] & !min[1] & min[4] & min[6] & !min[7] & !min[5] & min[8] & min[11] & !min[10] & !min[9] & min[12] & min[14] & !min[15] & !min[13] & min[17];
min[17]_or_out = min[17]_p1_out # min[17]_p2_out # min[17]_p4_out;
min[17]_reg_input = min[17]_or_out;
min[17] = TFFE(min[17]_reg_input, !sec, , , );


--count[12] is count[12] at LC33
count[12]_p1_out = count[11] & count[10] & count[9] & count[8] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[0] & count[1];
count[12]_or_out = count[12];
count[12]_reg_input = count[12]_p1_out $ count[12]_or_out;
count[12] = DFFE(count[12]_reg_input, !GLOBAL(clk), , , );


--min[18] is min[18] at LC30
min[18]_p1_out = min[16] & min[17] & min[0] & min[3] & !min[2] & !min[1] & min[4] & min[6] & !min[7] & !min[5] & min[8] & min[11] & !min[10] & !min[9] & min[12] & min[14] & !min[15] & !min[13];
min[18]_or_out = min[18]_p1_out;
min[18]_reg_input = min[18]_or_out;
min[18] = TFFE(min[18]_reg_input, !sec, , , );


--min[20] is min[20] at LC23
min[20]_p1_out = min[0] & min[3] & !min[2] & !min[1] & min[4] & min[6] & !min[7] & !min[5] & min[8] & min[11] & !min[10] & !min[9] & min[12] & min[14] & !min[15] & !min[13] & min[16] & min[19] & !min[18] & !min[17];
min[20]_or_out = min[20]_p1_out;
min[20]_reg_input = min[20]_or_out;
min[20] = TFFE(min[20]_reg_input, !sec, , , );


--min[23] is min[23] at LC24
min[23]_p1_out = min[22] & min[20] & min[21] & min[0] & min[3] & !min[2] & !min[1] & min[4] & min[6] & !min[7] & !min[5] & min[8] & min[11] & !min[10] & !min[9] & min[12] & min[14] & !min[15] & !min[13] & min[16] & min[19] & !min[18] & !min[17];
min[23]_or_out = min[23]_p1_out;
min[23]_reg_input = min[23]_or_out;
min[23] = TFFE(min[23]_reg_input, !sec, , , );


--min[22] is min[22] at LC25
min[22]_p1_out = !min[23] & min[20] & min[0] & min[3] & !min[2] & !min[1] & min[4] & min[6] & !min[7] & !min[5] & min[8] & min[11] & !min[10] & !min[9] & min[12] & min[14] & !min[15] & !min[13] & min[16] & min[19] & !min[18] & !min[17] & min[22];
min[22]_p2_out = min[20] & min[0] & min[3] & !min[2] & !min[1] & min[4] & min[6] & !min[7] & !min[5] & min[8] & min[11] & !min[10] & !min[9] & min[12] & min[14] & !min[15] & !min[13] & min[16] & min[19] & !min[18] & !min[17] & min[21];
min[22]_or_out = min[22]_p1_out # min[22]_p2_out;
min[22]_reg_input = min[22]_or_out;
min[22] = TFFE(min[22]_reg_input, !sec, , , );


--A1L2 is Select~1551 at LC50
A1L2_p0_out = count[12] & !count[11] & !count[10] & min[16];
A1L2_p1_out = min[0] & !count[12] & !count[11] & !count[10];
A1L2_p2_out = !count[12] & count[11] & count[10] & min[12];
A1L2_p3_out = !count[12] & count[11] & !count[10] & min[8];
A1L2_p4_out = count[12] & !count[11] & count[10] & min[20];
A1L2_or_out = A1L6 # A1L2_p0_out # A1L2_p1_out # A1L2_p2_out # A1L2_p3_out # A1L2_p4_out;
A1L2 = A1L2_or_out;


--A1L56 is ldsel_reg[0]~106 at LC123
A1L56_p2_out = A1L56 & count[12] & count[11];
A1L56_p3_out = A1L56 & count[12] & count[10];
A1L56_p4_out = count[12] & !count[11] & count[10];
A1L56_or_out = A1L66 # GND # GND # A1L56_p2_out # A1L56_p3_out # A1L56_p4_out;
A1L56 = A1L56_or_out;


--A1L76 is ldsel_reg[1]~110 at LC121
A1L76_p2_out = A1L76 & count[12] & count[11];
A1L76_p3_out = A1L76 & count[12] & !count[11] & !count[10];
A1L76_p4_out = count[12] & !count[11] & !count[10];
A1L76_or_out = GND # A1L76_p2_out # A1L76_p3_out # A1L76_p4_out;
A1L76 = A1L76_or_out;


--A1L86 is ldsel_reg[2]~114 at LC120
A1L86_p1_out = !count[12] & count[11] & count[10];
A1L86_p2_out = A1L86 & count[12] & count[11];
A1L86_p3_out = A1L86 & !count[12] & count[11] & count[10];
A1L86_or_out = A1L86_p1_out # A1L86_p2_out # A1L86_p3_out # GND;
A1L86 = A1L86_or_out;


--A1L96 is ldsel_reg[3]~118 at LC117
A1L96_p1_out = !count[12] & count[11] & !count[10];
A1L96_p2_out = A1L96 & count[12] & count[11];
A1L96_p3_out = A1L96 & !count[12] & count[11] & !count[10];
A1L96_or_out = A1L96_p1_out # A1L96_p2_out # A1L96_p3_out # GND;
A1L96 = A1L96_or_out;


--A1L07 is ldsel_reg[4]~122 at LC115
A1L07_p1_out = !count[12] & !count[11] & count[10];
A1L07_p2_out = A1L07 & count[12] & count[11];
A1L07_p3_out = A1L07 & !count[12] & !count[11] & count[10];
A1L07_p4_out = !count[12] & !count[11] & count[10];
A1L07_or_out = A1L07_p1_out # A1L07_p2_out # A1L07_p3_out # A1L07_p4_out;
A1L07 = A1L07_or_out;


--A1L17 is ldsel_reg[5]~126 at LC113
A1L17_p1_out = !count[12] & !count[11] & !count[10];
A1L17_p2_out = A1L17 & count[12] & count[11];
A1L17_p3_out = A1L17 & !count[12] & !count[11] & !count[10];
A1L17_p4_out = !count[12] & !count[11] & !count[10];
A1L17_or_out = A1L17_p1_out # A1L17_p2_out # A1L17_p3_out # A1L17_p4_out;
A1L17 = A1L17_or_out;


--A1L4 is Select~1553 at LC18
A1L4_p0_out = count[12] & !count[11] & !count[10] & min[18];
A1L4_p1_out = min[14] & !count[12] & count[11] & count[10];
A1L4_p2_out = !count[12] & !count[11] & !count[10] & min[2];
A1L4_p3_out = !count[12] & count[11] & !count[10] & min[10];
A1L4_p4_out = count[12] & !count[11] & count[10] & min[22];
A1L4_or_out = A1L7 # A1L4_p0_out # A1L4_p1_out # A1L4_p2_out # A1L4_p3_out # A1L4_p4_out;
A1L4 = A1L4_or_out;


--A1L5 is Select~1554 at LC20
A1L5_p0_out = count[12] & !count[11] & !count[10] & min[19];
A1L5_p1_out = min[15] & !count[12] & count[11] & count[10];
A1L5_p2_out = !count[12] & !count[11] & !count[10] & min[3];
A1L5_p3_out = !count[12] & !count[11] & count[10] & min[7];
A1L5_p4_out = count[12] & !count[11] & count[10] & min[23];
A1L5_or_out = A1L8 # A1L5_p0_out # A1L5_p1_out # A1L5_p2_out # A1L5_p3_out # A1L5_p4_out;
A1L5 = A1L5_or_out;


--min[21] is min[21] at LC29
min[21]_p1_out = !min[22] & min[20] & min[0] & min[3] & !min[2] & !min[1] & min[4] & min[6] & !min[7] & !min[5] & min[8] & min[11] & !min[10] & !min[9] & min[12] & min[14] & !min[15] & !min[13] & min[16] & min[19] & !min[18] & !min[17];
min[21]_p2_out = min[20] & min[0] & min[3] & !min[2] & !min[1] & min[4] & min[6] & !min[7] & !min[5] & min[8] & min[11] & !min[10] & !min[9] & min[12] & min[14] & !min[15] & !min[13] & min[16] & min[19] & !min[18] & !min[17] & min[23];
min[21]_p4_out = min[20] & min[0] & min[3] & !min[2] & !min[1] & min[4] & min[6] & !min[7] & !min[5] & min[8] & min[11] & !min[10] & !min[9] & min[12] & min[14] & !min[15] & !min[13] & min[16] & min[19] & !min[18] & !min[17] & min[21];
min[21]_or_out = min[21]_p1_out # min[21]_p2_out # min[21]_p4_out;
min[21]_reg_input = min[21]_or_out;
min[21] = TFFE(min[21]_reg_input, !sec, , , );


--A1L37 is ledbuf[0]~68 at LC70
A1L37_p1_out = A1L2 & A1L27;
A1L37_p2_out = A1L37 & count[12] & count[11];
A1L37_p3_out = A1L2 & A1L37;
A1L37_or_out = A1L37_p1_out # A1L37_p2_out # A1L37_p3_out;
A1L37 = A1L37_or_out;


--A1L57 is ledbuf[2]~72 at LC69
A1L57_p1_out = A1L4 & A1L27;
A1L57_p2_out = A1L57 & count[12] & count[11];
A1L57_p3_out = A1L4 & A1L57;
A1L57_or_out = A1L57_p1_out # A1L57_p2_out # A1L57_p3_out;
A1L57 = A1L57_or_out;


--A1L67 is ledbuf[3]~76 at LC68
A1L67_p1_out = A1L5 & A1L27;
A1L67_p2_out = A1L67 & count[12] & count[11];
A1L67_p3_out = A1L5 & A1L67;
A1L67_or_out = A1L67_p1_out # A1L67_p2_out # A1L67_p3_out;
A1L67 = A1L67_or_out;


--A1L3 is Select~1552 at LC22
A1L3_p0_out = count[12] & !count[11] & !count[10] & min[17];
A1L3_p1_out = min[13] & !count[12] & count[11] & count[10];
A1L3_p2_out = !count[12] & !count[11] & !count[10] & min[1];
A1L3_p3_out = !count[12] & !count[11] & count[10] & min[5];
A1L3_p4_out = count[12] & !count[11] & count[10] & min[21];
A1L3_or_out = A1L9 # A1L3_p0_out # A1L3_p1_out # A1L3_p2_out # A1L3_p3_out # A1L3_p4_out;
A1L3 = A1L3_or_out;


--A1L47 is ledbuf[1]~80 at LC67
A1L47_p1_out = A1L3 & A1L27;
A1L47_p2_out = A1L47 & count[12] & count[11];
A1L47_p3_out = A1L3 & A1L47;
A1L47_or_out = A1L47_p1_out # A1L47_p2_out # A1L47_p3_out;
A1L47 = A1L47_or_out;


--A1L301 is reduce_or~411 at LC76
A1L301_p1_out = !A1L47 & !A1L57;
A1L301_or_out = A1L301_p1_out # !A1L67;
A1L301 = A1L301_or_out;