led6.tan.qmsg

通过VERILOG HDL语言使用CPLD连接PS2键盘.

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 4 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register lpm_counter:count_rtl_0\|dffs\[13\] register lpm_counter:count_rtl_0\|dffs\[20\] 97.09 MHz 10.3 ns Internal " "Info: Clock \"clock\" has Internal fmax of 97.09 MHz between source register \"lpm_counter:count_rtl_0\|dffs\[13\]\" and destination register \"lpm_counter:count_rtl_0\|dffs\[20\]\" (period= 10.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.800 ns + Longest register register " "Info: + Longest register to register delay is 5.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:count_rtl_0\|dffs\[13\] 1 REG LC29 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC29; Fanout = 15; REG Node = 'lpm_counter:count_rtl_0\|dffs\[13\]'" {  } { { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "" { lpm_counter:count_rtl_0|dffs[13] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.100 ns) 5.800 ns lpm_counter:count_rtl_0\|dffs\[20\] 2 REG LC8 8 " "Info: 2: + IC(2.700 ns) + CELL(3.100 ns) = 5.800 ns; Loc. = LC8; Fanout = 8; REG Node = 'lpm_counter:count_rtl_0\|dffs\[20\]'" {  } { { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "5.800 ns" { lpm_counter:count_rtl_0|dffs[13] lpm_counter:count_rtl_0|dffs[20] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.100 ns 53.45 % " "Info: Total cell delay = 3.100 ns ( 53.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns 46.55 % " "Info: Total interconnect delay = 2.700 ns ( 46.55 % )" {  } {  } 0}  } { { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "5.800 ns" { lpm_counter:count_rtl_0|dffs[13] lpm_counter:count_rtl_0|dffs[20] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.800 ns" { lpm_counter:count_rtl_0|dffs[13] lpm_counter:count_rtl_0|dffs[20] } { 0.000ns 2.700ns } { 0.000ns 3.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock 1 CLK PIN_87 28 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 28; CLK Node = 'clock'" {  } { { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "" { clock } "NODE_NAME" } "" } } { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns lpm_counter:count_rtl_0\|dffs\[20\] 2 REG LC8 8 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC8; Fanout = 8; REG Node = 'lpm_counter:count_rtl_0\|dffs\[20\]'" {  } { { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "0.900 ns" { clock lpm_counter:count_rtl_0|dffs[20] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "3.400 ns" { clock lpm_counter:count_rtl_0|dffs[20] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[20] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.400 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock 1 CLK PIN_87 28 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 28; CLK Node = 'clock'" {  } { { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "" { clock } "NODE_NAME" } "" } } { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns lpm_counter:count_rtl_0\|dffs\[13\] 2 REG LC29 15 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC29; Fanout = 15; REG Node = 'lpm_counter:count_rtl_0\|dffs\[13\]'" {  } { { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "0.900 ns" { clock lpm_counter:count_rtl_0|dffs[13] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "3.400 ns" { clock lpm_counter:count_rtl_0|dffs[13] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[13] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0}  } { { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "3.400 ns" { clock lpm_counter:count_rtl_0|dffs[20] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[20] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "3.400 ns" { clock lpm_counter:count_rtl_0|dffs[13] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[13] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0}  } { { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "5.800 ns" { lpm_counter:count_rtl_0|dffs[13] lpm_counter:count_rtl_0|dffs[20] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.800 ns" { lpm_counter:count_rtl_0|dffs[13] lpm_counter:count_rtl_0|dffs[20] } { 0.000ns 2.700ns } { 0.000ns 3.100ns } } } { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "3.400 ns" { clock lpm_counter:count_rtl_0|dffs[20] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[20] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "3.400 ns" { clock lpm_counter:count_rtl_0|dffs[13] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[13] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock seg\[3\] lpm_counter:count_rtl_0\|dffs\[24\] 13.700 ns register " "Info: tco from clock \"clock\" to destination pin \"seg\[3\]\" through register \"lpm_counter:count_rtl_0\|dffs\[24\]\" is 13.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.400 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock 1 CLK PIN_87 28 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 28; CLK Node = 'clock'" {  } { { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "" { clock } "NODE_NAME" } "" } } { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns lpm_counter:count_rtl_0\|dffs\[24\] 2 REG LC1 25 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC1; Fanout = 25; REG Node = 'lpm_counter:count_rtl_0\|dffs\[24\]'" {  } { { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "0.900 ns" { clock lpm_counter:count_rtl_0|dffs[24] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "3.400 ns" { clock lpm_counter:count_rtl_0|dffs[24] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[24] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.700 ns + Longest register pin " "Info: + Longest register to pin delay is 8.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:count_rtl_0\|dffs\[24\] 1 REG LC1 25 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 25; REG Node = 'lpm_counter:count_rtl_0\|dffs\[24\]'" {  } { { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "" { lpm_counter:count_rtl_0|dffs[24] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(4.400 ns) 7.100 ns reduce_or~1129 2 COMB LC16 1 " "Info: 2: + IC(2.700 ns) + CELL(4.400 ns) = 7.100 ns; Loc. = LC16; Fanout = 1; COMB Node = 'reduce_or~1129'" {  } { { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "7.100 ns" { lpm_counter:count_rtl_0|dffs[24] reduce_or~1129 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 8.700 ns seg\[3\] 3 PIN PIN_92 0 " "Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 8.700 ns; Loc. = PIN_92; Fanout = 0; PIN Node = 'seg\[3\]'" {  } { { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "1.600 ns" { reduce_or~1129 seg[3] } "NODE_NAME" } "" } } { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 2 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 68.97 % " "Info: Total cell delay = 6.000 ns ( 68.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns 31.03 % " "Info: Total interconnect delay = 2.700 ns ( 31.03 % )" {  } {  } 0}  } { { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "8.700 ns" { lpm_counter:count_rtl_0|dffs[24] reduce_or~1129 seg[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.700 ns" { lpm_counter:count_rtl_0|dffs[24] reduce_or~1129 seg[3] } { 0.000ns 2.700ns 0.000ns } { 0.000ns 4.400ns 1.600ns } } }  } 0}  } { { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "3.400 ns" { clock lpm_counter:count_rtl_0|dffs[24] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[24] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" "" { Report "C:/altera/quartus50/six SMG/db/led6_cmp.qrpt" Compiler "led6" "UNKNOWN" "V1" "C:/altera/quartus50/six SMG/db/led6.quartus_db" { Floorplan "C:/altera/quartus50/six SMG/" "" "8.700 ns" { lpm_counter:count_rtl_0|dffs[24] reduce_or~1129 seg[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.700 ns" { lpm_counter:count_rtl_0|dffs[24] reduce_or~1129 seg[3] } { 0.000ns 2.700ns 0.000ns } { 0.000ns 4.400ns 1.600ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 06 00:16:18 2007 " "Info: Processing ended: Fri Jul 06 00:16:18 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}