fashe.map.qmsg

通过VERILOG HDL语言使用CPLD连接PS2键盘.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jul 06 00:20:44 2007 " "Info: Processing started: Fri Jul 06 00:20:44 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fashe -c fashe " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fashe -c fashe" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fashe.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fashe.v" { { "Info" "ISGN_ENTITY_NAME" "1 fashe " "Info: Found entity 1: fashe" {  } { { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "fashe " "Info: Elaborating entity \"fashe\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 fashe.v(15) " "Warning: Verilog HDL assignment warning at fashe.v(15): truncated value with size 32 to match size of target (11)" {  } { { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 15 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 fashe.v(16) " "Warning: Verilog HDL assignment warning at fashe.v(16): truncated value with size 32 to match size of target (1)" {  } { { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 16 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 fashe.v(20) " "Warning: Verilog HDL assignment warning at fashe.v(20): truncated value with size 32 to match size of target (11)" {  } { { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 20 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 fashe.v(21) " "Warning: Verilog HDL assignment warning at fashe.v(21): truncated value with size 32 to match size of target (1)" {  } { { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 21 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 fashe.v(28) " "Warning: Verilog HDL assignment warning at fashe.v(28): truncated value with size 32 to match size of target (4)" {  } { { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 28 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 fashe.v(30) " "Warning: Verilog HDL assignment warning at fashe.v(30): truncated value with size 32 to match size of target (4)" {  } { { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 30 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 fashe.v(34) " "Warning: Verilog HDL assignment warning at fashe.v(34): truncated value with size 32 to match size of target (1)" {  } { { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 34 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 fashe.v(43) " "Warning: Verilog HDL assignment warning at fashe.v(43): truncated value with size 32 to match size of target (1)" {  } { { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 43 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 fashe.v(44) " "Warning: Verilog HDL assignment warning at fashe.v(44): truncated value with size 32 to match size of target (1)" {  } { { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 44 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "count\[0\]~11 11 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=11) from the following logic: \"count\[0\]~11\"" {  } { { "fashe.v" "count\[0\]~11" { Text "C:/altera/quartus50/uart_send/fashe.v" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clock " "Info: Promoted clock signal driven by pin \"clock\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "19 " "Info: Implemented 19 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "17 " "Info: Implemented 17 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 06 00:20:46 2007 " "Info: Processing ended: Fri Jul 06 00:20:46 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}