fashe.tan.qmsg

通过VERILOG HDL语言使用CPLD连接PS2键盘.

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "bit_start " "Info: Detected ripple clock \"bit_start\" as buffer" {  } { { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "bit_start" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register bitcnt_reg\[1\] register txd_reg 97.09 MHz 10.3 ns Internal " "Info: Clock \"clock\" has Internal fmax of 97.09 MHz between source register \"bitcnt_reg\[1\]\" and destination register \"txd_reg\" (period= 10.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.800 ns + Longest register register " "Info: + Longest register to register delay is 5.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bitcnt_reg\[1\] 1 REG LC4 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4; Fanout = 7; REG Node = 'bitcnt_reg\[1\]'" {  } { { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "" { bitcnt_reg[1] } "NODE_NAME" } "" } } { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.100 ns) 5.800 ns txd_reg 2 REG LC109 1 " "Info: 2: + IC(2.700 ns) + CELL(3.100 ns) = 5.800 ns; Loc. = LC109; Fanout = 1; REG Node = 'txd_reg'" {  } { { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "5.800 ns" { bitcnt_reg[1] txd_reg } "NODE_NAME" } "" } } { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.100 ns 53.45 % " "Info: Total cell delay = 3.100 ns ( 53.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns 46.55 % " "Info: Total interconnect delay = 2.700 ns ( 46.55 % )" {  } {  } 0}  } { { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "5.800 ns" { bitcnt_reg[1] txd_reg } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.800 ns" { bitcnt_reg[1] txd_reg } { 0.000ns 2.700ns } { 0.000ns 3.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 9.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 9.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock 1 CLK PIN_87 12 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 12; CLK Node = 'clock'" {  } { { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "" { clock } "NODE_NAME" } "" } } { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns bit_start 2 REG LC5 5 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC5; Fanout = 5; REG Node = 'bit_start'" {  } { { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "2.500 ns" { clock bit_start } "NODE_NAME" } "" } } { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.200 ns) 9.900 ns txd_reg 3 REG LC109 1 " "Info: 3: + IC(2.700 ns) + CELL(2.200 ns) = 9.900 ns; Loc. = LC109; Fanout = 1; REG Node = 'txd_reg'" {  } { { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "4.900 ns" { bit_start txd_reg } "NODE_NAME" } "" } } { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns 72.73 % " "Info: Total cell delay = 7.200 ns ( 72.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns 27.27 % " "Info: Total interconnect delay = 2.700 ns ( 27.27 % )" {  } {  } 0}  } { { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "9.900 ns" { clock bit_start txd_reg } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { clock clock~out bit_start txd_reg } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 9.900 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 9.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock 1 CLK PIN_87 12 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 12; CLK Node = 'clock'" {  } { { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "" { clock } "NODE_NAME" } "" } } { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns bit_start 2 REG LC5 5 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC5; Fanout = 5; REG Node = 'bit_start'" {  } { { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "2.500 ns" { clock bit_start } "NODE_NAME" } "" } } { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.200 ns) 9.900 ns bitcnt_reg\[1\] 3 REG LC4 7 " "Info: 3: + IC(2.700 ns) + CELL(2.200 ns) = 9.900 ns; Loc. = LC4; Fanout = 7; REG Node = 'bitcnt_reg\[1\]'" {  } { { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "4.900 ns" { bit_start bitcnt_reg[1] } "NODE_NAME" } "" } } { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns 72.73 % " "Info: Total cell delay = 7.200 ns ( 72.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns 27.27 % " "Info: Total interconnect delay = 2.700 ns ( 27.27 % )" {  } {  } 0}  } { { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "9.900 ns" { clock bit_start bitcnt_reg[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { clock clock~out bit_start bitcnt_reg[1] } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0}  } { { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "9.900 ns" { clock bit_start txd_reg } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { clock clock~out bit_start txd_reg } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "9.900 ns" { clock bit_start bitcnt_reg[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { clock clock~out bit_start bitcnt_reg[1] } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 7 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 5 -1 0 } }  } 0}  } { { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "5.800 ns" { bitcnt_reg[1] txd_reg } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.800 ns" { bitcnt_reg[1] txd_reg } { 0.000ns 2.700ns } { 0.000ns 3.100ns } } } { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "9.900 ns" { clock bit_start txd_reg } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { clock clock~out bit_start txd_reg } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "9.900 ns" { clock bit_start bitcnt_reg[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { clock clock~out bit_start bitcnt_reg[1] } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock txd txd_reg 13.100 ns register " "Info: tco from clock \"clock\" to destination pin \"txd\" through register \"txd_reg\" is 13.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 9.900 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 9.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock 1 CLK PIN_87 12 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 12; CLK Node = 'clock'" {  } { { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "" { clock } "NODE_NAME" } "" } } { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns bit_start 2 REG LC5 5 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC5; Fanout = 5; REG Node = 'bit_start'" {  } { { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "2.500 ns" { clock bit_start } "NODE_NAME" } "" } } { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.200 ns) 9.900 ns txd_reg 3 REG LC109 1 " "Info: 3: + IC(2.700 ns) + CELL(2.200 ns) = 9.900 ns; Loc. = LC109; Fanout = 1; REG Node = 'txd_reg'" {  } { { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "4.900 ns" { bit_start txd_reg } "NODE_NAME" } "" } } { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns 72.73 % " "Info: Total cell delay = 7.200 ns ( 72.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns 27.27 % " "Info: Total interconnect delay = 2.700 ns ( 27.27 % )" {  } {  } 0}  } { { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "9.900 ns" { clock bit_start txd_reg } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { clock clock~out bit_start txd_reg } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 5 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.600 ns + Longest register pin " "Info: + Longest register to pin delay is 1.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns txd_reg 1 REG LC109 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC109; Fanout = 1; REG Node = 'txd_reg'" {  } { { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "" { txd_reg } "NODE_NAME" } "" } } { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns txd 2 PIN PIN_71 0 " "Info: 2: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_71; Fanout = 0; PIN Node = 'txd'" {  } { { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "1.600 ns" { txd_reg txd } "NODE_NAME" } "" } } { "fashe.v" "" { Text "C:/altera/quartus50/uart_send/fashe.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns 100.00 % " "Info: Total cell delay = 1.600 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "1.600 ns" { txd_reg txd } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.600 ns" { txd_reg txd } { 0.000ns 0.000ns } { 0.000ns 1.600ns } } }  } 0}  } { { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "9.900 ns" { clock bit_start txd_reg } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { clock clock~out bit_start txd_reg } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" "" { Report "C:/altera/quartus50/uart_send/db/fashe_cmp.qrpt" Compiler "fashe" "UNKNOWN" "V1" "C:/altera/quartus50/uart_send/db/fashe.quartus_db" { Floorplan "C:/altera/quartus50/uart_send/" "" "1.600 ns" { txd_reg txd } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.600 ns" { txd_reg txd } { 0.000ns 0.000ns } { 0.000ns 1.600ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 06 00:20:55 2007 " "Info: Processing ended: Fri Jul 06 00:20:55 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}