read_write.txt

uart pci 等verilog hdl 代码

module read_write(read_in,read_out,address_contr,addre_adder,data_rin,data_readout,clk,wri_in,wri_out,data_win,data_wri);
input read_in;
input clk;
input wri_in;
input [7:0] data_rin;
input [7:0] data_win;
input [15:0] addre_adder;
output wri_out;
output [15:0] address_contr;
output [7:0] data_readout;
output readout;
output [7:0] data_wri;

assign address_contr=0;

always begin
		read_out=0;
		wri_out=0;
	
		always@(wri_in) begin
		wri_out=wri_in;
		if(wri_in) begin
		address_contr=address_contr+15'b1;
		data_wri=data_win;
					end 
						end
						
		
		always@(read_in) begin
		read_out=read_in;
		if(read_in) begin
					always@(posedge clk)
					address_contr=address_contr+addre_adder;
					data_readout=data_rin;				
					end
						 end
		end				
endmodule