📄 eda.rpt
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_EQ008 = _LC1_B13 & _LC7_B13
# _LC1_B13 & !_LC8_B18
# !EN & _LC1_B13
# EN & !_LC1_B13 & !_LC7_B13 & _LC8_B18;
-- Node name is '|JS:1|:25' = '|JS:1|tmpb0'
-- Equation name is '_LC3_B18', type is buried
_LC3_B18 = DFFE( _EQ009, GLOBAL( CLK), !CLR, VCC, VCC);
_EQ009 = !EN & _LC3_B18
# EN & !_LC3_B18;
-- Node name is '|JS:1|:24' = '|JS:1|tmpb1'
-- Equation name is '_LC5_B18', type is buried
_LC5_B18 = DFFE( _EQ010, GLOBAL( CLK), !CLR, VCC, VCC);
_EQ010 = _LC3_B18 & _LC5_B18 & !_LC8_B18
# EN & !_LC3_B18 & !_LC5_B18 & !_LC8_B18
# !EN & _LC5_B18;
-- Node name is '|JS:1|:23' = '|JS:1|tmpb2'
-- Equation name is '_LC7_B18', type is buried
_LC7_B18 = DFFE( _EQ011, GLOBAL( CLK), !CLR, VCC, VCC);
_EQ011 = _LC6_B18 & _LC7_B18 & !_LC8_B18
# EN & !_LC6_B18 & !_LC7_B18 & !_LC8_B18
# !EN & _LC7_B18;
-- Node name is '|JS:1|:22' = '|JS:1|tmpb3'
-- Equation name is '_LC4_B18', type is buried
_LC4_B18 = DFFE( _EQ012, GLOBAL( CLK), !CLR, VCC, VCC);
_EQ012 = _LC4_B18 & _LC7_B18
# _LC4_B18 & _LC6_B18
# EN & !_LC4_B18 & !_LC6_B18 & !_LC7_B18
# !EN & _LC4_B18;
-- Node name is '|JS:1|:38'
-- Equation name is '_LC6_B13', type is buried
_LC6_B13 = LCELL( _EQ013);
_EQ013 = !_LC1_B13 & !_LC7_B13 & _LC8_B18;
-- Node name is '|JS:1|:76'
-- Equation name is '_LC8_B18', type is buried
_LC8_B18 = LCELL( _EQ014);
_EQ014 = !_LC4_B18 & !_LC6_B18 & !_LC7_B18;
-- Node name is '|QDJB:2|:127'
-- Equation name is '_LC3_B8', type is buried
!_LC3_B8 = _LC3_B8~NOT;
_LC3_B8~NOT = LCELL( _EQ015);
_EQ015 = D
# C
# B
# !A;
-- Node name is '|QDJB:2|:137'
-- Equation name is '_LC4_B8', type is buried
_LC4_B8 = LCELL( _EQ016);
_EQ016 = !A & B & !C & !D;
-- Node name is '|QDJB:2|:147'
-- Equation name is '_LC1_B8', type is buried
!_LC1_B8 = _LC1_B8~NOT;
_LC1_B8~NOT = LCELL( _EQ017);
_EQ017 = A
# B
# !C
# D;
-- Node name is '|QDJB:2|:157'
-- Equation name is '_LC8_B5', type is buried
!_LC8_B5 = _LC8_B5~NOT;
_LC8_B5~NOT = LCELL( _EQ018);
_EQ018 = !D
# _LC2_B8;
-- Node name is '|QDJB:2|~168~1'
-- Equation name is '_LC2_B8', type is buried
-- synthesized logic cell
_LC2_B8 = LCELL( _EQ019);
_EQ019 = C
# A
# B;
-- Node name is '|QDJB:2|:298'
-- Equation name is '_LC7_B5', type is buried
_LC7_B5 = LCELL( _EQ020);
_EQ020 = _LC6_B5 & _LC7_B5
# CLR & _LC7_B5
# !CLR & _LC3_B8;
-- Node name is '|QDJB:2|:313'
-- Equation name is '_LC5_B24', type is buried
_LC5_B24 = LCELL( _EQ021);
_EQ021 = _LC4_B8
# !_LC1_B8 & _LC1_B24 & _LC4_B24;
-- Node name is '|QDJB:2|~315~1'
-- Equation name is '_LC4_B24', type is buried
-- synthesized logic cell
_LC4_B24 = LCELL( _LC2_B8);
-- Node name is '|QDJB:2|:319'
-- Equation name is '_LC1_B24', type is buried
_LC1_B24 = LCELL( _EQ022);
_EQ022 = _LC2_B13 & _LC5_B24
# CLR & _LC1_B24;
-- Node name is '|QDJB:2|~321~1'
-- Equation name is '_LC2_B13', type is buried
-- synthesized logic cell
_LC2_B13 = LCELL( _EQ023);
_EQ023 = !CLR & !_LC3_B8;
-- Node name is '|QDJB:2|:331'
-- Equation name is '_LC2_B18', type is buried
_LC2_B18 = LCELL( _EQ024);
_EQ024 = _LC1_B18 & _LC2_B8
# _LC1_B8;
-- Node name is '|QDJB:2|:340'
-- Equation name is '_LC1_B18', type is buried
_LC1_B18 = LCELL( _EQ025);
_EQ025 = _LC3_B24
# CLR & _LC1_B18;
-- Node name is '|QDJB:2|:342'
-- Equation name is '_LC3_B24', type is buried
_LC3_B24 = LCELL( _EQ026);
_EQ026 = _LC2_B13 & _LC2_B18 & !_LC4_B8;
-- Node name is '|QDJB:2|:349'
-- Equation name is '_LC5_B5', type is buried
_LC5_B5 = LCELL( _EQ027);
_EQ027 = D & !_LC2_B8
# D & _LC4_B5
# _LC2_B8 & _LC4_B5;
-- Node name is '|QDJB:2|:361'
-- Equation name is '_LC4_B5', type is buried
_LC4_B5 = LCELL( _EQ028);
_EQ028 = !CLR & _LC2_B5 & _LC5_B5
# CLR & _LC4_B5;
-- Node name is '|QDJB:2|:382'
-- Equation name is '_LC3_B5', type is buried
_LC3_B5 = LCELL( _EQ029);
_EQ029 = !CLR & _LC2_B5 & _LC3_B5 & !_LC8_B5;
-- Node name is '|QDJB:2|:403'
-- Equation name is '_LC1_B16', type is buried
_LC1_B16 = LCELL( _EQ030);
_EQ030 = !CLR & _LC1_B16 & _LC2_B5
# !CLR & _LC2_B5 & _LC8_B5;
-- Node name is '|QDJB:2|~405~1'
-- Equation name is '_LC2_B5', type is buried
-- synthesized logic cell
_LC2_B5 = LCELL( _EQ031);
_EQ031 = !_LC1_B8 & !_LC3_B8 & !_LC4_B8;
-- Node name is '|QDJB:2|~405~2'
-- Equation name is '_LC7_B24', type is buried
-- synthesized logic cell
!_LC7_B24 = _LC7_B24~NOT;
_LC7_B24~NOT = LCELL( _EQ032);
_EQ032 = _LC4_B8
# _LC1_B8;
-- Node name is '|QDJB:2|:424'
-- Equation name is '_LC2_B24', type is buried
_LC2_B24 = LCELL( _EQ033);
_EQ033 = _LC2_B13 & !_LC7_B24
# _LC2_B13 & _LC2_B24 & !_LC8_B5;
-- Node name is '|QDJB:2|:436'
-- Equation name is '_LC6_B24', type is buried
_LC6_B24 = LCELL( _EQ034);
_EQ034 = !_LC8_B5 & _LC8_B24
# _LC1_B8;
-- Node name is '|QDJB:2|:445'
-- Equation name is '_LC8_B24', type is buried
_LC8_B24 = LCELL( _EQ035);
_EQ035 = !CLR & !_LC4_B8 & _LC6_B24
# !CLR & _LC3_B8;
-- Node name is '|QDJB:2|:466'
-- Equation name is '_LC1_B5', type is buried
_LC1_B5 = LCELL( _EQ036);
_EQ036 = !CLR & _LC1_B5
# !CLR & _LC8_B5
# !CLR & !_LC2_B5;
Project Information d:\ccw\eda.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 11,401K
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