📄 eda.rpt
字号:
23 - - B -- OUTPUT 0 1 0 0 D1
71 - - A -- OUTPUT 0 1 0 0 QA0
70 - - A -- OUTPUT 0 1 0 0 QA1
69 - - A -- OUTPUT 0 1 0 0 QA2
67 - - B -- OUTPUT 0 1 0 0 QA3
66 - - B -- OUTPUT 0 1 0 0 QB0
65 - - B -- OUTPUT 0 1 0 0 QB1
64 - - B -- OUTPUT 0 1 0 0 QB2
62 - - C -- OUTPUT 0 1 0 0 QB3
24 - - B -- OUTPUT 0 1 0 0 SP
27 - - C -- OUTPUT 0 1 0 0 SPEAKER
79 - - - 24 OUTPUT 0 1 0 0 STATES0
78 - - - 24 OUTPUT 0 1 0 0 STATES1
73 - - A -- OUTPUT 0 1 0 0 STATES2
72 - - A -- OUTPUT 0 1 0 0 STATES3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\ccw\eda.rpt
eda
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - B 05 AND2 s 0 3 0 1 CLR~1
- 3 - B 13 AND2 s 1 1 0 1 EN~1
- 7 - B 13 AND2 ! 0 3 0 2 |JS:1|LPM_ADD_SUB:85|addcore:adder|pcarry2
- 6 - B 18 AND2 ! 0 2 0 3 |JS:1|LPM_ADD_SUB:90|addcore:adder|pcarry1
- 1 - B 13 DFFE + 2 2 1 1 |JS:1|tmpa3 (|JS:1|:18)
- 8 - B 13 DFFE + 1 3 1 1 |JS:1|tmpa2 (|JS:1|:19)
- 5 - B 13 DFFE + ! 2 2 1 2 |JS:1|tmpa1 (|JS:1|:20)
- 4 - B 13 DFFE + 2 1 1 3 |JS:1|tmpa0 (|JS:1|:21)
- 4 - B 18 DFFE + 2 2 1 1 |JS:1|tmpb3 (|JS:1|:22)
- 7 - B 18 DFFE + 2 2 1 2 |JS:1|tmpb2 (|JS:1|:23)
- 5 - B 18 DFFE + 2 2 1 1 |JS:1|tmpb1 (|JS:1|:24)
- 3 - B 18 DFFE + 2 0 1 2 |JS:1|tmpb0 (|JS:1|:25)
- 6 - B 13 AND2 0 3 1 0 |JS:1|:38
- 8 - B 18 AND2 0 3 0 7 |JS:1|:76
- 3 - B 08 OR2 ! 4 0 0 4 |QDJB:2|:127
- 4 - B 08 AND2 4 0 0 6 |QDJB:2|:137
- 1 - B 08 OR2 ! 4 0 0 6 |QDJB:2|:147
- 8 - B 05 OR2 ! 1 1 0 5 |QDJB:2|:157
- 2 - B 08 OR2 s 3 0 0 5 |QDJB:2|~168~1
- 7 - B 05 OR2 1 2 1 0 |QDJB:2|:298
- 5 - B 24 OR2 0 4 0 1 |QDJB:2|:313
- 4 - B 24 AND2 s 0 1 0 1 |QDJB:2|~315~1
- 1 - B 24 OR2 1 2 1 1 |QDJB:2|:319
- 2 - B 13 AND2 s 1 1 0 3 |QDJB:2|~321~1
- 2 - B 18 OR2 0 3 0 1 |QDJB:2|:331
- 1 - B 18 OR2 1 1 1 1 |QDJB:2|:340
- 3 - B 24 AND2 0 3 0 1 |QDJB:2|:342
- 5 - B 05 OR2 1 2 0 1 |QDJB:2|:349
- 4 - B 05 OR2 1 2 1 1 |QDJB:2|:361
- 3 - B 05 AND2 1 2 1 0 |QDJB:2|:382
- 1 - B 16 OR2 1 2 1 0 |QDJB:2|:403
- 2 - B 05 AND2 s 0 3 0 4 |QDJB:2|~405~1
- 7 - B 24 OR2 s ! 0 2 0 1 |QDJB:2|~405~2
- 2 - B 24 OR2 0 3 1 0 |QDJB:2|:424
- 6 - B 24 OR2 0 3 0 1 |QDJB:2|:436
- 8 - B 24 OR2 1 3 1 1 |QDJB:2|:445
- 1 - B 05 OR2 1 2 1 0 |QDJB:2|:466
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\ccw\eda.rpt
eda
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 1/ 48( 2%) 4/ 48( 8%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
B: 16/ 96( 16%) 3/ 48( 6%) 6/ 48( 12%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 3/ 96( 3%) 1/ 48( 2%) 1/ 48( 2%) 3/16( 18%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 4/24( 16%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\ccw\eda.rpt
eda
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 CLK
Device-Specific Information: d:\ccw\eda.rpt
eda
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 17 CLR
Device-Specific Information: d:\ccw\eda.rpt
eda
** EQUATIONS **
A : INPUT;
B : INPUT;
C : INPUT;
CLK : INPUT;
CLR : INPUT;
D : INPUT;
EN : INPUT;
-- Node name is 'A1'
-- Equation name is 'A1', type is output
A1 = _LC7_B5;
-- Node name is 'B1'
-- Equation name is 'B1', type is output
B1 = _LC1_B24;
-- Node name is 'CLR~1'
-- Equation name is 'CLR~1', location is LC6_B5, type is buried.
-- synthesized logic cell
_LC6_B5 = LCELL( _EQ001);
_EQ001 = !_LC1_B8 & _LC2_B8 & !_LC4_B8;
-- Node name is 'C1'
-- Equation name is 'C1', type is output
C1 = _LC1_B18;
-- Node name is 'D1'
-- Equation name is 'D1', type is output
D1 = _LC4_B5;
-- Node name is 'EN~1'
-- Equation name is 'EN~1', location is LC3_B13, type is buried.
-- synthesized logic cell
_LC3_B13 = LCELL( _EQ002);
_EQ002 = EN & _LC8_B18;
-- Node name is 'QA0'
-- Equation name is 'QA0', type is output
QA0 = _LC4_B13;
-- Node name is 'QA1'
-- Equation name is 'QA1', type is output
QA1 = _LC5_B13;
-- Node name is 'QA2'
-- Equation name is 'QA2', type is output
QA2 = _LC8_B13;
-- Node name is 'QA3'
-- Equation name is 'QA3', type is output
QA3 = _LC1_B13;
-- Node name is 'QB0'
-- Equation name is 'QB0', type is output
QB0 = _LC3_B18;
-- Node name is 'QB1'
-- Equation name is 'QB1', type is output
QB1 = _LC5_B18;
-- Node name is 'QB2'
-- Equation name is 'QB2', type is output
QB2 = _LC7_B18;
-- Node name is 'QB3'
-- Equation name is 'QB3', type is output
QB3 = _LC4_B18;
-- Node name is 'SP'
-- Equation name is 'SP', type is output
SP = _LC6_B13;
-- Node name is 'SPEAKER'
-- Equation name is 'SPEAKER', type is output
SPEAKER = _LC1_B5;
-- Node name is 'STATES0'
-- Equation name is 'STATES0', type is output
STATES0 = _LC8_B24;
-- Node name is 'STATES1'
-- Equation name is 'STATES1', type is output
STATES1 = _LC2_B24;
-- Node name is 'STATES2'
-- Equation name is 'STATES2', type is output
STATES2 = _LC1_B16;
-- Node name is 'STATES3'
-- Equation name is 'STATES3', type is output
STATES3 = _LC3_B5;
-- Node name is '|JS:1|LPM_ADD_SUB:85|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC7_B13', type is buried
!_LC7_B13 = _LC7_B13~NOT;
_LC7_B13~NOT = LCELL( _EQ003);
_EQ003 = !_LC4_B13 & !_LC5_B13 & !_LC8_B13;
-- Node name is '|JS:1|LPM_ADD_SUB:90|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_B18', type is buried
!_LC6_B18 = _LC6_B18~NOT;
_LC6_B18~NOT = LCELL( _EQ004);
_EQ004 = !_LC3_B18 & !_LC5_B18;
-- Node name is '|JS:1|:21' = '|JS:1|tmpa0'
-- Equation name is '_LC4_B13', type is buried
_LC4_B13 = DFFE( _EQ005, GLOBAL( CLK), !CLR, VCC, VCC);
_EQ005 = _LC4_B13 & !_LC8_B18
# EN & !_LC4_B13 & _LC8_B18
# !EN & _LC4_B13;
-- Node name is '|JS:1|:20' = '|JS:1|tmpa1'
-- Equation name is '_LC5_B13', type is buried
!_LC5_B13 = _LC5_B13~NOT;
_LC5_B13~NOT = DFFE( _EQ006, GLOBAL( CLK), !CLR, VCC, VCC);
_EQ006 = _LC4_B13 & !_LC5_B13
# !_LC5_B13 & !_LC8_B18
# !EN & !_LC5_B13
# EN & !_LC4_B13 & _LC5_B13 & _LC8_B18;
-- Node name is '|JS:1|:19' = '|JS:1|tmpa2'
-- Equation name is '_LC8_B13', type is buried
_LC8_B13 = DFFE( _EQ007, GLOBAL( CLK), !CLR, VCC, VCC);
_EQ007 = _LC5_B13 & _LC8_B13
# _LC4_B13 & _LC8_B13
# !_LC3_B13 & _LC8_B13
# _LC3_B13 & !_LC4_B13 & !_LC5_B13 & !_LC8_B13;
-- Node name is '|JS:1|:18' = '|JS:1|tmpa3'
-- Equation name is '_LC1_B13', type is buried
_LC1_B13 = DFFE( _EQ008, GLOBAL( CLK), !CLR, VCC, VCC);
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -