sl1_basic_op.h

定点除法器程序

 *  \param p1 a pointer map to address register(INT32 *)
 *  \param am1 ar mode of \a p1, see AR_MODE
 *  \param p2 a pointer map to address register(INT32 *)
 *  \param am2 ar mode of \a p2, see AR_MODE
 *  \param mode see ACC_MODE
 *  \param shr unsigned immediate integer, should be in range of (0, 31)
 *  \return result(INT32)
 *  \note if p1 and p2 acquired address registers before <br>
            c3.dmulan.a acc, acc1, mode, p1, am1, p2, am2, 0 <br>
            c3.mvfs rd, acc, shr                             <br>
          else <br>
            c3.mvts ar1, p1, 0      <br>
            c3.mvts ar2, p2, 0      <br>
            c3.dmulan.a acc, acc1, mode, p1, am1, p2, am2, 0 <br>
            c3.mvfs rd, acc, shr    <br>
            c3.mvfs p1, ar1, 0      <br>
            c3.mvfs p2, ar2, 0      <br>

 */
#define _sl1_l_dmultn_shr_p(p1, am1, p2, am2, mode, shr) \
  SL1_L_dmul_shr_p(0, mode, p1, am1, p2, am2, 0, shr)


/*! \def _sl1_l_dmultn_p(L_acc, p1, am1, p2, am2, mode)
 *  \brief a macro that do dual multiply by address registers with different mode and store the negated value to \a L_acc
 *   update address of \a p1 and \a p2 according with \a ar1 and \a ar2
 *  \param L_acc variable(INT32), prefer to acquire dual acc registers
 *  \param p1 a pointer map to address register(INT32 *)
 *  \param am1 ar mode of \a p1, see AR_MODE
 *  \param p2 a pointer map to address register(INT32 *)
 *  \param am2 ar mode of \a p2, see AR_MODE
 *  \param mode see ACC_MODE
 *  \return result(INT32)
 *  \note if L_acc acquired acc and p1/p2 acquired address register <br>
            c3.dmulan.a L_acc, acc1, mode,  p1, am1, p2, am2, 0 <br>
          else <br>
            c3.mvts acc, L_acc, shr <br>
            c3.mvts acc1, 0, 0   <br>
            c3.mvts ar1, p1, 0   <br>
            c3.mvts ar2, p2, 0   <br>
            c3.dmulan.a acc, acc1, mode, ar1, am1, ar2, am2, 0 <br>
            c3.mvfs rd, acc, 0   <br>
            c3.mvfs p1, ar1, 0   <br>
            c3.mvfs p2, ar2, 0   <br>
 */
#define _sl1_l_dmultn_p(L_acc, p1, am1, p2, am2, mode) \
  SL1_L_dmuln_shr_p(L_acc, mode, p1, am1, p2, am2, 0, 0)


/*! \def _sl1_l_acquire_acc(L_var1)
 *  \brief a macro that acquire an acc register and initialize it with \a L_var1
 *  \param L_var1 variable(INT32)
 *  \return result(INT32)
 *  \note used with "_sl1_l_free_acc/_sl1_l_shr_free_acc" at the same time
 */
#define _sl1_l_acquire_acc(L_var1) \
  SL1_L_acquire_acc(L_var1, 0)

/*! \def _sl1_l_shl_acquire_acc(L_var1, shl) 
 *  \brief a macro that acquire an acc register and initialize it with shift left \a L_var1 by \a shl
 *  \param L_var1 variable(INT32)
 *  \param shl unsigned immediate integer, should be in range of (0, 31)
 *  \return result(INT32)
 *  \note used with "_sl1_l_free_acc/_sl1_l_shr_free_acc" at the same time
 */
#define _sl1_l_shl_acquire_acc(L_var1, shl) \
  SL1_L_acquire_acc(L_var1, shl)

/*! \def _sl1_l_free_acc(L_var1)
 *  \brief a macro that copy value of acc register, free the acc register at the same time
 *  \param L_var1 variable(INT32) acquired an acc register
 *  \return result(INT32)
 *  \note used with "_sl1_l_require_acc/_sl1_l_shl_acquire_acc" at the same time
 */
#define _sl1_l_free_acc(L_var1) \
  SL1_L_free_acc(L_var1, 0)


/*! \def _sl1_l_shr_free_acc(L_var1, shr)
 *  \brief a macro that shift right the value of acc register by \a shr and copy out, free the acc register at the same time
 *  \param L_var1 variable(INT32) acquired an acc register
 *  \param shr unsigned immediate integer, should be in range of (0, 31)
 *  \note used with "_sl1_l_require_acc/_sl1_l_shl_acquire_acc" at the same time
 *  \return result(INT32)
 */
#define _sl1_l_shr_free_acc(L_var1, shr) \
  SL1_L_free_acc(L_var1, shr)
  
/*! \def _sl1_l_copy_shr_acc(L_var1, shr)
 *  \brief a macro that shift right the value of acc register by \a shr and copy out the temporary value 
 *  \param L_var1 variable(INT32) acquired an acc register
 *  \param shr unsigned immediate integer, should be in range of (0, 31)
 *  \return result(INT32)
 */
#define _sl1_l_copy_shr_acc(L_var1, shr) \
  SL1_L_copy_shr_acc(L_var1, shr, 0)


/*! \def _sl1_l_copy_shr_dacc_1st(L_var1, shr)
 *  \brief a macro that shift right even acc value of dual acc registers by \a shr and copy out
 *  \param L_var1 variable(INT32) acquired dual acc registers
 *  \param shr unsigned immediate integer, should be in range of (0, 31)
 *  \return result(INT32)
 */
#define _sl1_l_copy_shr_dacc_1st(L_var1, shr) \
  SL1_L_copy_shr_acc(L_var1, shr, 0)


/*! \def _sl1_l_copy_shr_dacc_2nd(L_var1, shr)
 *  \brief a macro that shift right odd acc value of dual acc registers by \a shr and copy out
 *  \param L_var1 variable(INT32) acquired dual acc registers
 *  \param shr unsigned immediate integer, should be in range of (0, 31)
 *  \return result(INT32)
 */
#define _sl1_l_copy_shr_dacc_2nd(L_var1, shr) \
  SL1_L_copy_shr_acc(L_var1, shr, 1)

  
/*! \def _sl1_l_acquire_dual_acc(L_var1)
 *  \brief a macro that acquire dual acc registers, even acc is initialized with \a L_var1 and odd acc is initialized with 0
 *  \param L_var1 variable(INT32) acquired dual acc registers
 *  \return result(INT32)
 *  \note used with "_sl1_l_free_dual_acc" 
 */
#define _sl1_l_acquire_dual_acc(L_var1) \
  SL1_L_acquire_dacc(L_var1, 0, 0, 0)



/*! \def _sl1_l_shl_acquire_dual_acc(L_var1, shl)
 *  \brief a macro that acquire dual acc registers, even acc is initialized with shift left \a L_var1 by \a shl  and odd acc is initialized with 0
 *  \param L_var1 variable(INT32) acquired dual acc registers
 *  \param shl1 unsigned immediate integer, should be in range of (0, 31)
 *  \param L_var2 variable(INT32) acquired odd acc registers
 *  \param shl2 unsigned immediate integer
 *  \return result(INT32)
 *  \note used with "_sl1_l_free_dual_acc/_sl1_l_sadd_free_dual_acc"
 *  \note mvts acc0, L_var1, shl1 <br>
          mvts acc1, L_var2, shl2 <br>
 */ 
#define _sl1_l_shl_acquire_dual_acc(L_var1, shl1, L_var2, shl2) \
  SL1_L_acquire_dacc(L_var1, shl1, L_var2, shl2)


/*! \def _sl1_l_free_dual_acc(L_var1)
 *  \brief a macro that copy out value of odd acc of dual acc registers
 *  \param L_var1 variable(INT32) acquired dual acc registers
 *  \return result(INT32)
 *  \note used with "_l_require_dual_acc" at the same time
 */
#define _sl1_l_free_dual_acc(L_var1) \
  SL1_L_free_dacc(L_var1, 0)  


/*! \def _sl1_l_sadd_free_dual_acc(L_var1)
 *  \brief a macro that add value of dual acc registers with saturation, free dual acc registers
 *  \param L_var1 variable(INT32) acquired dual acc registers
 *  \return result(INT32)
 *  \note used with "_l_require_dual_acc" at the same time
 */
#define _sl1_l_sadd_free_dual_acc(L_var1) \
  SL1_L_free_dacc(L_var1, 1)


/*! \def _sl1_acquire_addr(p1)
 *  \brief a macro that acquire an address register and initialize it with p1
 *  \param p1 variable
 *  \return result
 *  \note used with "_sl1_free_addr" at the same time
 */
#define _sl1_acquire_addr(p1)  \
  SL1_acquire_addr(p1, 0)


/*! \def _sl1_free_addr(p1)
 *  \brief a macro that copy out the address register and free it
 *  \param p1 variable acquired an address register
 *  \return result
 *  \note used with "_sl1_require_addr" at the same time
 */
#define _sl1_free_addr(p1) \
  SL1_free_addr(p1)


/*! \def _sl1_set_addr_size(p1, update_size)
 *  \brief a macro that set address updated size register
 *  \param p1 variable acquired an address register
 *  \param update_size unsigned immediate integer
 *  \return no result
 *  \note if p1 is (INT16 *), and you want to do p1+2, the update_size should be 2(step)*2(byte)=4,
      and if p1 is (INT32 *), and you want to do p1+2, the update_size should be 2(step)*4(byte)=8, etc.
 */
#define _sl1_set_addr_size(p1, update_size) \
  SL1_set_addr(p1, update_size)


/*! \def _sl1_fft_load(p1, dtype)
 *  \brief a macro that load a data from memory based on update size register and bank index
 *  \param p1 variable acquired an address register
 *  \param dtype size of data to be loaded
 *  \return result 
 *  \note if p1 acquired address register before <br> 
            c3.fftld rd, p1, AR_I1, dtype  <br>
          else <br>
            c3.mvts ar1, p1, 0  <br>
            c3.fftld rd, ar1, AR_I1, dtype <br>
            c3.mvfs p1, ar1, 0  <br>
 */
#define _sl1_fft_load(p1, dtype) \
  SL1_fft_load(p1, 1, dtype, 0)

/*! \def _sl1_fft_store(L_var1, p1, dtype)
 *  \brief a macro that store \a L_var1 into memory based on update size register and bank index
 *  \param L_var1 variable to be stored
 *  \param p1 variable acquired an address register
 *  \param dtype size of the data to be stored
 *  \return no result(void)
 *  \note if p1 acquired address register before <br>
             c3.fftst L_var1, p1, AR_I1, dtype  <br>
          else <br> 
             c3.mvts ar1, p1, 0  <br>
             c3.fftst L_var1, ar1, AR_I1, dtype <br>
             c3.mvfs p1, ar1, 0  <br>
 */
#define _sl1_fft_store(L_var1, p1, dtype)  \
  SL1_fft_store(L_var1, p1, 1, dtype, 0)

/*! \def _sl1_load(p1, am1, dtype)
 *  \brief a macro that load a data from memory with address updating
 *  \param p1 variable acquired an address register
 *  \param am1 ar mode of \a p1
 *  \param dtype size of data to be loaded
 *  \return result
 *  \note if p1 acquired address register before <br>
            c3.ld rd, p1, am1, dtype  <br>
          else <br>
            c3.mvts ar1, p1, 0  <br>
            c3.ld rd, ar1, am1, dtype <br>
            c3.mvfs p1, ar1, 0  <br>
 */
#define _sl1_load(p1, am1, dtype) \
  SL1_load(p1, am1, dtype, 0)


/*! \def _sl1_store(L_var1, p1, am1, dtype)
 *  \brief a macro that store \a L_var1 to memory with address updating
 *  \param L_var1 variable to be stored
 *  \param p1 variable acquired an address register
 *  \param am1 ar mode of \a p1
 *  \param dtype size of data to be stored
 *  \return no result(void)
 *  \note if p1 acquired address register before <br>
             c3.st L_var1, p1, am1, dtype  <br>
          else <br>
             c3.mvts ar1, p1, 0  <br>
             c3.st L_var1, ar1, am1, dtype <br>
             c3.mvfs p1, ar1, 0  <br>
 */
#define _sl1_store(L_var1, p1, am1, dtype) \
  SL1_store(L_var1, p1, am1, dtype, 0)


/*! \def _sl1_l_dmac(L_acc, rs1, rs2, mode)
 *  \brief a macro that do dual mac
 *  \param L_acc variable(INT32), prefer to acquire dual acc registers
 *  \param rs1 variable(INT32)
 *  \param rs2 variable(INT32)
 *  \param mode see ACC_MODE
 *  \return result(INT32) 
 *  \note if L_acc acquired dual acc registers <br>
            c3.dmac L_acc, L_acc1, acm, rs1, rs2, 0  <br>
          else <br>
            c3.mvts acc, L_acc, 0   <br>
            c3.mvts acc1, 0, 0      <br>
            c3.dmac acc, acc1, acm, rs1, rs2, 0  <br>
            c3.mvfs tmp0, acc, 0    <br>
            c3.mvfs tmp1, acc1, 0   <br>
            c3.saadds rd, tmp0, tmp1 <br>
 */
#define _sl1_l_dmac(L_acc, rs1, rs2, mode) \
  SL1_L_dmac(L_acc, mode, rs1, rs2, 0)


/*! \def _sl1_l_dmac_sub(L_acc, rs1, rs2, mode)
 *  \brief a macro that do mac in even acc and msu in odd acc
 *  \param L_acc variable(INT32), prefer to acquire dual acc registers
 *  \param rs1 variable(INT32)
 *  \param rs2 variable(INT32)
 *  \param mode see ACC_MODE
 *  \return result(INT32)
 *  \note see _sl1_l_dmac
 */
#define _sl1_l_dmac_sub(L_acc, rs1, rs2, mode) \
  SL1_L_dmac(L_acc, mode, rs1, rs2, 1)


/*! \def _sl1_l_dmacn(L_acc, rs1, rs2, mode)
 *  \brief a macro that do dual msu 
 *  \param L_acc variable(INT32), prefer to acquire dual acc registers
 *  \param rs1 variable(INT32)
 *  \param rs2 variable(INT32)
 *  \param mode see ACC_MODE
 *  \return result(INT32)
 *  \note if L_acc acquired dual acc registers <br>
            c3.dmacn L_acc, L_acc1, acm, rs1, rs2, 0  <br>
          else <br>
            c3.mvts acc, L_acc, 0   <br>
            c3.mvts acc1, 0, 0      <br>
            c3.dmacn acc, acc1, acm, rs1, rs2, 0  <br>
            c3.mvfs tmp0, acc, 0    <br>
            c3.mvfs tmp1, acc1, 0   <br>
            c3.saadds rd, tmp0, tmp1 <br>
 */
#define _sl1_l_dmacn(L_acc, rs1, rs2, mode) \
  SL1_L_dmacn(L_acc, mode, rs1, rs2, 0)


/*! \def _sl1_l_dmacn_add(L_acc, rs1, rs2, mode)
 *  \brief a macro that do msu in even acc and mac in odd acc 
 *  \param L_acc variable(INT32), prefer to acquire dual acc registers
 *  \param rs1 variable(INT32)
 *  \param rs2 variable(INT32)
 *  \param mode see ACC_MODE
 *  \note see _sl1_l_dmacn
 */
#define _sl1_l_dmacn_add(L_acc, rs1, rs2, mode) \
  SL1_L_dmacn(L_acc, mode, rs1, rs2, 1)


/*! \def _sl1_deposit(L_rd, L_var1, pos, width)
 *  \brief a macro that deposit bits from source GPR to destination GPR
 *  \param L_rd destination variable(INT32)
 *  \param L_var1 source variable(INT32)
 *  \param pos unsigned immediate
 *  \param width unsigned immediate
 *  \return variable(INT32) 
 *  GPR[rd][pos:pos-width+1] =  GPR[rs1][width-1:0];
 * GPR[rd][pos-width:0] = GPR[rd][pos-width:0];
 * GPR[rd][31:pos+1] =  GPR[rd][31:pos+1];
 *  \note depb L_rd, L_var1, pos, width
 */
#define _sl1_deposit(L_rd, L_var1, pos, width) \
  SL1_deposit(L_rd, L_var1, pos, width)


/*! \def _sl1_extract(L_var1, pos, width)
 *  \brief a macro that extract bits from source GPR to destination GPR <br>
           rd = sign_ext(GPR[L_var1][pos:pos-width+1])
 *  \param L_var1 source variable(INT32)
 *  \param pos unsigned immediate 
 *  \param width unsigned immediate