sl1_basic_op.h

定点除法器程序

 *  \param var1 variable(INT16)
 *  \param var2 variable(INT16)
 *  \param mode see ACC_MODE
 *  \return result(INT32)
 *  \note if L_acc acquired an acc register before <br>
             c3.mac  L_acc, mode,var1, var2   <br>
          else <br>
             c3.mvts acc, L_acc, 0 <br>
             c3.mac acc, mode, var1, var2 <br>
             c3.mvfs L_acc, acc, 0 <br>
 */
#define _sl1_l_mac(L_acc, var1, var2, mode) \
  SL1_L_mac(L_acc, var1, var2, mode)


/*! \def _sl1_l_mac_p(L_acc, p1, am1, p2, am2, mode) 
 *  \brief a macro that multiply two 16 bits variable loaded from address registers and add with L_acc with different mode,
 *   update address of \a p1 and \a p2 according with \a ar1 and \a ar2
 *  \param L_acc variable(INT32), prefer to acquire an acc register
 *  \param p1 a pointer map to address register(INT16 *)
 *  \param am1 ar mode of \a p1
 *  \param p2 a pointer map to address register(INT16 *)
 *  \param am2 ar mode of \a p2 
 *  \param mode see ACC_MODE
 *  \return result(INT32)
 *  \note if L_acc acquired acc register before && p1/p2 acquired address registers before <br>
            c3.mac.a  L_acc, mode, p1, am1, p2, am2, 0 <br>
          else <br>
            c3.mvts acc, L_acc, 0 <br>
            c3.mvts ar1, p1,  0   <br>
            c3.mvts ar2, p2, 0    <br>
            c3.mac.a acc, mode, ar1, am1, ar2, am2, 0 <br>
            c3.mvfs rd, acc, 0    <br>
            c3.mvfs p1, ar1, 0    <br>
            c3.mvfs p2, ar2, 0    <br>
 */
#define _sl1_l_mac_p(L_acc, p1, am1, p2, am2, mode) \
  SL1_L_mac_p(L_acc, mode, p1, am1, p2, am2, 0)

/*! \def _sl1_l_smac_shl1_p(L_acc, p1, am1, p2, am2)
 *  \brief a macro that multiply two 16 bits variable loaded from address registers and add with \a L_acc with saturation and shift left by 1,
 *   update address of p1 and p2 according with ar1 and ar2 
 *  \param L_acc variable(INT32), prefer to acquire an acc register
 *  \param p1 a pointer map to address register(INT16 *)
 *  \param am1 ar mode of \a p1
 *  \param p2 a pointer map to address register(INT16 *)
 *  \param am2 ar mode of \a p2
 *  \return result(INT32)
 *  \note if L_acc acquired acc register before && p1/p2 acquired address registers before <br>
            c3.mac.a  L_acc, 3, p1, am1, p2, am2, 0 <br>
          else <br>
            c3.mvts acc, L_acc, 0 <br>
            c3.mvts ar1, p1,  0   <br>
            c3.mvts ar2, p2, 0    <br>
            c3.mac.a acc, 3, ar1, am1, ar2, am2, 0 <br>
            c3.mvfs rd, acc, 0    <br>
            c3.mvfs p1, ar1, 0    <br>
            c3.mvfs p2, ar2, 0    <br>
 */
#define _sl1_l_smac_shl1_p(L_acc, p1, am1, p2, am2) \
  SL1_L_mac_p(L_acc, (ACC_SAT|ACC_SHF), p1, am1, p2, am2, 0)
  
  
/*! \def _sl1_l_mac_v_p(L_acc, var1, p2, am2, mode) 
 *  \brief a macro that multiply \a var1 and variable loaded from address register and add to \a L_acc with different mode,
 *   update address of p2 according with am2
 *  \param L_acc variable(INT32), prefer to acquire an acc register
 *  \param var1 variable(INT16)
 *  \param p2 a pointer map to address register(INT16 *)
 *  \param am2 ar mode of \a p2
 *  \param mode see ACC_MODE
 *  \return result(INT32)
    \note if L_acc acquired acc register before && p1 acquired an address register before <br>
             c3.mac.ar L_acc, mode, var1, p2, ar2, 0 <br>
          else <br>
            c3.mvts acc, L_acc, 0 <br>
            c3.mvts ar2, p2, 0    <br>
            c3.mac.a acc, mode, var1, ar2, am2, 0 <br>
            c3.mvfs rd, acc, 0    <br>
            c3.mvfs p2, ar2, 0    <br>
 */
#define _sl1_l_mac_v_p(L_acc, var1, p2, am2, mode)      \
  SL1_L_mac_v_p(L_acc, mode, var1, p2, am2, 0)


/*! \def _sl1_l_msu(L_acc, var1, var2, mode) 
 *  \brief a macro that multiply \a var1 and \a var2 and substract by \a L_acc with different mode,
 *   update address of \a p1 and \a p2 according with \a ar1 and \a ar2
 *  \param L_acc variable(INT32), prefer to acquire an acc register
 *  \param var1 variable(INT16)
 *  \param var2 variable(INT16)
 *  \param mode see ACC_MODE
 *  \return result(INT32)
 *  \note if L_acc acquired an acc register before <br>
             c3.macn  L_acc, mode,var1, var2   <br>
          else <br>
             c3.mvts acc, L_acc, 0 <br>
             c3.macn acc, mode, var1, var2 <br>
             c3.mvfs L_acc, acc, 0 <br>
 */
#define _sl1_l_msu(L_acc, var1, var2, mode) \
  SL1_L_msu(L_acc, var1, var2, mode)


/*! \def _sl1_l_msu_p(L_acc, p1, am1, p2, am2, mode)
 *  \brief a macro that multiply two variable loaded from address registers and substract by \a L_acc with different mode,
 *   update address of p1 and p2 according with ar1 and ar2
 *  \param L_acc variable(INT32), prefer to acquire an acc register
 *  \param p1 a pointer map to address register(INT16 *)
 *  \param am1 ar mode of \a p1
 *  \param p2 a pointer map to address register(INT16 *)
 *  \param am2 ar mode of \a p2
 *  \param mode see ACC_MODE
 *  \return result(INT32)
 *  \note if L_acc acquired acc register before && p1/p2 acquired address registers before <br>
            c3.macn.a  L_acc, mode, p1, am1, p2, am2, 0 <br>
          else <br>
            c3.mvts acc, L_acc, 0 <br>
            c3.mvts ar1, p1,  0   <br>
            c3.mvts ar2, p2, 0    <br>
            c3.macn.a acc, mode, ar1, am1, ar2, am2, 0 <br>
            c3.mvfs rd, acc, 0    <br>
            c3.mvfs p1, ar1, 0    <br>
            c3.mvfs p2, ar2, 0    <br>
 */
#define _sl1_l_msu_p(L_acc, p1, am1, p2, am2, mode) \
  SL1_L_msu_p(L_acc, mode, p1, am1, p2, am2, 0)


/*! \def _sl1_l_msu_v_p(L_acc, var1, p2, am2, mode)
 *  \brief a macro that multiply \a var1 and variable loaded from address register and substract by \a L_acc with different mode,
 *   update address of p2 according with ar2
 *  \param L_acc variable(INT32), prefer to acquire an acc register
 *  \param var1 variable(INT16)
 *  \param p2 a pointer map to address register(INT16 *)
 *  \param am2 ar mode of \a p2
 *  \param mode see ACC_MODE
 *  \return result(INT32)
    \note if L_acc acquired acc register before && p1 acquired an address register before <br>
             c3.mac.ar L_acc, mode, var1, p2, ar2, 0 <br>
          else <br>
            c3.mvts acc, L_acc, 0 <br>
            c3.mvts ar2, p2, 0    <br>
            c3.mac.a acc, mode, var1, ar2, am2, 0 <br>
            c3.mvfs rd, acc, 0    <br>
            c3.mvfs p2, ar2, 0    <br>
 */
#define _sl1_l_msu_v_p(L_acc, var1, p2, am2, mode) \
  SL1_L_msu_v_p(L_acc, mode, var1, p2, am2, 0)


/*! \def _sl1_l_dmac_p(L_acc, p1, am1, p2, am2, mode)
 *  \brief a macro that do dual mac by address registers with different mode, update address of \a p1 and \a p2 according with \a ar1 and \a ar2
 *  \param L_acc variable(INT32), prefer to acquire dual acc registers
 *  \param p1 a pointer map to address register(INT32 *)
 *  \param am1 ar mode of \a p1
 *  \param p2 a pointer map to address register(INT32 *)
 *  \param am2 ar mode of \a p2
 *  \param mode see ACC_MODE
 *  \return result(INT32)
 *  \note if L_acc acquired dual acc registers before && p1/p2 acquired address registers before <br>
            c3.dmac.a  L_acc, L_acc1, mode, p1, am1, p2, am2, 0 <br>
          else <br>
            c3.mvts acc, L_acc, 0 <br>
            c3.mvts acc1, 0, 0    <br>
            c3.mvts ar1, p1,  0   <br>
            c3.mvts ar2, p2, 0    <br>
            c3.dmac.a acc, acc1, mode, ar1, am1, ar2, am2, 0 <br>
            c3.mvfs tmp1, acc, 0    <br>
            c3.mvfs tmp2, acc1, 0   <br>
            c3.saadds rd, tmp1, tmp2 <br> 
            c3.mvfs p1, ar1, 0    <br>
            c3.mvfs p2, ar2, 0    <br>
 */
#define _sl1_l_dmac_p(L_acc, p1, am1, p2, am2, mode) \
  SL1_L_dmac_p(L_acc, mode, p1, am1, p2, am2, 0, 0)


/*! \def _sl1_l_dmac_sub_p(L_acc, p1, ar1, p2, ar2, mode)
 *  \brief a macro that do mac in even acc and msu in odd acc by address registers with different mode,
 *   update address of \a p1 and \a p2 according with \a ar1 and \a ar2
 *  \param L_acc variable(INT32), prefer to acquire dual acc registers
 *  \param p1 a pointer map to address register(INT32 *)
 *  \param ar1 ar mode of \a p1
 *  \param p2 a pointer map to address register(INT32 *)
 *  \param ar2 ar mode of \a p2
 *  \param mode see ACC_MODE
 *  \return result(INT32)
 *  \note see _sl1_l_dmac_p
 */
#define _sl1_l_dmac_sub_p(L_acc, p1, ar1, p2, ar2, mode) \
  SL1_L_dmac_p(L_acc, mode, p1, ar1, p2, ar2, 0, 1)
  
/*! \def _sl1_l_dmacn_p(L_acc, p1, am1, p2, am2, mode)
 *  \brief a macro that do dual negated mac by address registers with different mode, 
 *   update address of \a p1 and \a p2 according with \a ar1 and \a ar2
 *  \param L_acc variable(INT32), prefer to acquire dual acc registers
 *  \param p1 a pointer map to address register(INT32 *)
 *  \param am1 ar mode of \a p1
 *  \param p2 a pointer map to address register(INT32 *)
 *  \param am2 ar mode of \a p2
 *  \param mode see ACC_MODE
 *  \return result(INT32)
 *  \note if L_acc acquired dual acc registers before && p1/p2 acquired address registers before <br>
            c3.dmacn.a  L_acc, L_acc1, mode, p1, am1, p2, am2, 0 <br>
          else <br>
            c3.mvts acc, L_acc, 0 <br>
            c3.mvts acc1, 0, 0    <br>
            c3.mvts ar1, p1,  0   <br>
            c3.mvts ar2, p2, 0    <br>
            c3.dmacn.a acc, acc1, mode, ar1, am1, ar2, am2, 0 <br>
            c3.mvfs tmp1, acc, 0    <br>
            c3.mvfs tmp2, acc1, 0   <br>
            c3.saadds rd, tmp1, tmp2 <br>
            c3.mvfs p1, ar1, 0    <br>
            c3.mvfs p2, ar2, 0    <br>
 */
#define _sl1_l_dmacn_p(L_acc, p1, am1, p2, am2, mode) \
  SL1_L_dmacn_p(L_acc, mode, p1, am1, p2, am2, 0, 0)

/*! \def _sl1_l_dmacn_add_p(L_acc, p1, am1, p2, am2, mode)
 *  \brief a macro that do msu in even acc and mac in odd acc with different mode, 
 *   update address of \a p1 and \a p2 according with \a ar1 and \a ar2
 *  \param L_acc variable(INT32), prefer to acquire dual acc registers
 *  \param p1 a pointer map to address register(INT32 *)
 *  \param am1 ar mode of \a p1, see AR_MODE
 *  \param p2 a pointer map to address register(INT32 *)
 *  \param am2 ar mode of \a p2, see AR_MODE
 *  \param mode see ACC_MODE
 *  \return result(INT32)
 *  \note see _sl1_l_dmacn_p
 */
#define _sl1_l_dmacn_add_p(L_acc, p1, am1, p2, am2, mode) \
  SL1_L_dmacn_p(L_acc, mode, p1, am1, p2, am2, 0, 1)


/*! \def _sl1_l_dmult_shr(var1, var2, mode, shr)
 *  \brief a macro that do dual multiply with different mode, shift the value by \a shr
 *  \param var1 variable(INT32)
 *  \param var2 variable(INT32)
 *  \param mode see ACC_MODE
 *  \param shr unsigned immediate integer, should be in range of (0,31)
 *  \return result(INT32)
 *  \note c3.dmula acc, acc1, mode, var1, var2  <br>
          c3.mvfs rd, acc, shr
 */
#define _sl1_l_dmult_shr(var1, var2, mode, shr) \
  SL1_dmul_shr(0, var1, var2, mode, shr)


/*! \def _sl1_l_dmult(L_acc, var1, var2, mode)
 *  \brief a macro that do dual multiply with different mode and store to \a L_acc
 *  \param L_acc variable(INT32), prefer to acquire dual acc registers
 *  \param var1 variable(INT32)
 *  \param var2 variable(INT32)
 *  \param mode see ACC_MODE
 *  \return result(INT32)	
 *  \note if L_acc acquired dual acc registers before <br>
            c3.dmula acc, acc1, mode, var1, var2  <br>
          else <br>
            c3.dmula acc, acc1, mode, var1, var2  <br>
            c3.mvfs rd, acc, 0
 */
#define _sl1_l_dmult(L_acc, var1, var2, mode) \
  SL1_dmul_shr(L_acc, var1, var2, mode, 0)


/*! \def _sl1_l_dmultn_shr(var1, var2, mode, shr)
 *  \brief a macro that do negated dual multiply with different mode, shift the value by \a shr
 *  \param var1 variable(INT32)
 *  \param var2 variable(INT32)
 *  \param mode see ACC_MODE
 *  \param shr unsigned immediate integer, should be in range of (0, 31) 
 *  \return result(INT32)
 *  \note c3.dmulan acc, acc1, mode, var1, var2  <br>
          c3.mvfs rd, acc, shr
 */
#define _sl1_l_dmultn_shr(var1, var2, mode, shr) \
  SL1_dmuln_shr(0, var1, var2, mode, shr)

/*! \def _sl1_l_dmultn(L_acc, var1, var2, mode)
 *  \brief a macro that do negated dual multiply with different mode and store to \a L_acc
 *  \param L_acc variable(INT32), prefer to acquire dual acc registers
 *  \param var1 variable(INT32)
 *  \param var2 variable(INT32)
 *  \param mode see ACC_MODE
 *  \return result(INT32)
 *  \note if L_acc acquired dual acc registers before <br>
            c3.dmulan acc, acc1, mode, var1, var2  <br>
          else <br>
            c3.dmulan acc, acc1, mode, var1, var2  <br>
            c3.mvfs rd, acc, 0
 */  
#define _sl1_l_dmultn(L_acc, var1, var2, mode) \
  SL1_dmuln_shr(L_acc, var1, var2, mode, 0)


/*! \def _sl1_l_dmult_shr_p(p1, am1, p2, am2, mode, shr)
 *  \brief a macro that do dual multiply by address registers with different mode, shift the value by \a shr
 *   update address of \a p1 and \a p2 according with \a ar1 and \a ar2
 *  \param p1 a pointer map to address register(INT32 *)
 *  \param am1 ar mode of \a p1, see AR_MODE
 *  \param p2 a pointer map to address register(INT32 *)
 *  \param am2 ar mode of \a p2, see AR_MODE
 *  \param mode see ACC_MODE
 *  \param shr unsigned immediate integer, should be in range of (0, 31)
 *  \return result(INT32) 
 *  \note if p1 and p2 acquired address registers before <br>
            c3.dmula.a acc, acc1, mode, p1, am1, p2, am2, 0 <br> 
            c3.mvfs rd, acc, shr                             <br>
          else <br>
            c3.mvts ar1, p1, 0      <br>
            c3.mvts ar2, p2, 0      <br>
            c3.dmula.a acc, acc1, mode, p1, am1, p2, am2, 0 <br>
            c3.mvfs rd, acc, shr    <br>
            c3.mvfs p1, ar1, 0      <br>
            c3.mvfs p2, ar2, 0      <br>
 */
#define _sl1_l_dmult_shr_p(p1, am1, p2, am2, mode, shr) \
  SL1_L_dmul_shr_p(0, mode, p1, am1, p2, am2, 0, shr)


/*! \def _sl1_l_dmult_p(L_acc, p1, am1, p2, am2, mode) 
 *  \brief a macro that do dual multiply by address registers with different mode and store to \a L_acc
 *   update address of \a p1 and \a p2 according with \a ar1 and \a ar2
 *  \param L_acc variable(INT32), prefer to acquire dual acc registers
 *  \param p1 a pointer map to address register(INT32 *)
 *  \param am1 ar mode of \a p1, see AR_MODE
 *  \param p2 a pointer map to address register(INT32 *)
 *  \param am2 ar mode of \a p2, see AR_MODE
 *  \param mode see ACC_MODE
 *  \return result(INT32)
 *  \note if L_acc acquired acc and p1/p2 acquired address register <br>
            c3.dmula.a L_acc, acc1, mode,  p1, am1, p2, am2, 0 <br>
          else <br>
            c3.mvts acc, L_acc, shr <br>
            c3.mvts acc1, 0, 0   <br> 
            c3.mvts ar1, p1, 0   <br>
            c3.mvts ar2, p2, 0   <br>
            c3.dmula.a acc, acc1, mode, ar1, am1, ar2, am2, 0 <br>
            c3.mvfs rd, acc, 0   <br>
            c3.mvfs p1, ar1, 0   <br>
            c3.mvfs p2, ar2, 0   <br>
 */
#define _sl1_l_dmult_p(L_acc, p1, am1, p2, am2, mode) \
  SL1_L_dmul_shr_p(L_acc, mode, p1, am1, p2, am2, 0, 0)


/*! \def _sl1_l_dmultn_shr_p(p1, am1, p2, am2, mode, shr)
 *  \brief a macro that do dual negative multiply by address registers with different mode, shift the negated value by \a shr
 *   update address of \a p1 and \a p2 according with \a ar1 and \a ar2