gewei.map.rpt

自己用VHDL写的键盘程序

+----------------------------------+-----------------+------------------------------------+--------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total combinational functions               ; 44    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 17    ;
;     -- 3 input functions                    ; 4     ;
;     -- <=2 input functions                  ; 23    ;
;         -- Combinational cells for routing  ; 0     ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 31    ;
;     -- arithmetic mode                      ; 13    ;
; Total registers                             ; 20    ;
; I/O pins                                    ; 17    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 16    ;
; Total fan-out                               ; 182   ;
; Average fan-out                             ; 2.25  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                            ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                   ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------+
; |gewei                     ; 44 (0)            ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 17   ; 0            ; |gewei                                ;
;    |divider:inst4|         ; 22 (22)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |gewei|divider:inst4                  ;
;    |geweictrl:inst|        ; 1 (1)             ; 4 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |gewei|geweictrl:inst                 ;
;       |geweidcfq:inst1|    ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |gewei|geweictrl:inst|geweidcfq:inst1 ;
;       |geweidcfq:inst2|    ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |gewei|geweictrl:inst|geweidcfq:inst2 ;
;       |geweidcfq:inst3|    ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |gewei|geweictrl:inst|geweidcfq:inst3 ;
;       |geweidcfq:inst|     ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |gewei|geweictrl:inst|geweidcfq:inst  ;
;    |geweidecord:inst19|    ; 16 (16)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |gewei|geweidecord:inst19             ;
;    |geweizd:inst2|         ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |gewei|geweizd:inst2                  ;
;    |zd4:inst3|             ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |gewei|zd4:inst3                      ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 20    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 4     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 9     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/vhdl_exe/fpga论文/gewei/gewei.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Apr 23 12:18:45 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off gewei -c gewei
Info: Found 2 design units, including 1 entities, in source file ../shiwei/dcfq.vhd
    Info: Found design unit 1: dcfq-one
    Info: Found entity 1: dcfq
Info: Found 1 design units, including 1 entities, in source file ../shiwei/ctrl.bdf
    Info: Found entity 1: ctrl
Warning: Can't analyze file -- file E:/vhdl_exe/fpga论文/gewei/dfq.vhd is missing
Warning: Can't analyze file -- file E:/vhdl_exe/fpga论文/gewei/ctrl.bdf is missing
Warning: Can't analyze file -- file E:/vhdl_exe/fpga论文/gewei/dcfq.vhd is missing
Warning: Can't analyze file -- file E:/vhdl_exe/fpga论文/gewei/zd.vhd is missing
Warning: Can't analyze file -- file E:/vhdl_exe/fpga论文/gewei/decord.vhd is missing
Info: Found 2 design units, including 1 entities, in source file zd4.vhd
    Info: Found design unit 1: zd4-one
    Info: Found entity 1: zd4
Info: Found 1 design units, including 1 entities, in source file gewei.bdf
    Info: Found entity 1: gewei
Info: Found 1 design units, including 1 entities, in source file geweictrl.bdf
    Info: Found entity 1: geweictrl
Info: Found 2 design units, including 1 entities, in source file divider.vhd
    Info: Found design unit 1: divider-one
    Info: Found entity 1: divider
Info: Elaborating entity "gewei" for the top level hierarchy
Warning: Port "out1" of type geweidecord and instance "inst19" is missing source signal
Info: Using design file geweizd.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: geweizd-one
    Info: Found entity 1: geweizd
Info: Elaborating entity "geweizd" for hierarchy "geweizd:inst2"
Warning: VHDL Process Statement warning at geweizd.vhd(14): signal "a" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Using design file geweidecord.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: geweidecord-one
    Info: Found entity 1: geweidecord
Info: Elaborating entity "geweidecord" for hierarchy "geweidecord:inst19"
Info: Elaborating entity "geweictrl" for hierarchy "geweictrl:inst"
Info: Using design file geweidcfq.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: geweidcfq-one
    Info: Found entity 1: geweidcfq
Info: Elaborating entity "geweidcfq" for hierarchy "geweictrl:inst|geweidcfq:inst"
Info: Elaborating entity "divider" for hierarchy "divider:inst4"
Info: Elaborating entity "zd4" for hierarchy "zd4:inst3"
Warning: VHDL Process Statement warning at zd4.vhd(14): signal "a" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Implemented 81 device resources after synthesis - the final resource count might be different
    Info: Implemented 12 input pins
    Info: Implemented 5 output pins
    Info: Implemented 64 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
    Info: Processing ended: Wed Apr 23 12:18:49 2008
    Info: Elapsed time: 00:00:04