gewei.fit.qmsg

自己用VHDL写的键盘程序

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.273 ns register register " "Info: Estimated most critical path is register to register delay of 3.273 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns divider:inst4\|count\[0\] 1 REG LAB_X19_Y26 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X19_Y26; Fanout = 3; REG Node = 'divider:inst4\|count\[0\]'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "" { divider:inst4|count[0] } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/divider.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.649 ns) + CELL(0.626 ns) 1.275 ns divider:inst4\|add~193 2 COMB LAB_X19_Y26 2 " "Info: 2: + IC(0.649 ns) + CELL(0.626 ns) = 1.275 ns; Loc. = LAB_X19_Y26; Fanout = 2; COMB Node = 'divider:inst4\|add~193'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "1.275 ns" { divider:inst4|count[0] divider:inst4|add~193 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.139 ns) 1.414 ns divider:inst4\|add~195 3 COMB LAB_X19_Y26 2 " "Info: 3: + IC(0.000 ns) + CELL(0.139 ns) = 1.414 ns; Loc. = LAB_X19_Y26; Fanout = 2; COMB Node = 'divider:inst4\|add~195'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "0.139 ns" { divider:inst4|add~193 divider:inst4|add~195 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.139 ns) 1.553 ns divider:inst4\|add~197 4 COMB LAB_X19_Y26 2 " "Info: 4: + IC(0.000 ns) + CELL(0.139 ns) = 1.553 ns; Loc. = LAB_X19_Y26; Fanout = 2; COMB Node = 'divider:inst4\|add~197'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "0.139 ns" { divider:inst4|add~195 divider:inst4|add~197 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.139 ns) 1.692 ns divider:inst4\|add~199 5 COMB LAB_X19_Y26 2 " "Info: 5: + IC(0.000 ns) + CELL(0.139 ns) = 1.692 ns; Loc. = LAB_X19_Y26; Fanout = 2; COMB Node = 'divider:inst4\|add~199'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "0.139 ns" { divider:inst4|add~197 divider:inst4|add~199 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.139 ns) 1.831 ns divider:inst4\|add~201 6 COMB LAB_X19_Y26 2 " "Info: 6: + IC(0.000 ns) + CELL(0.139 ns) = 1.831 ns; Loc. = LAB_X19_Y26; Fanout = 2; COMB Node = 'divider:inst4\|add~201'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "0.139 ns" { divider:inst4|add~199 divider:inst4|add~201 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.516 ns) 2.347 ns divider:inst4\|add~202 7 COMB LAB_X19_Y26 1 " "Info: 7: + IC(0.000 ns) + CELL(0.516 ns) = 2.347 ns; Loc. = LAB_X19_Y26; Fanout = 1; COMB Node = 'divider:inst4\|add~202'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "0.516 ns" { divider:inst4|add~201 divider:inst4|add~202 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.180 ns) + CELL(0.636 ns) 3.163 ns divider:inst4\|count~166 8 COMB LAB_X19_Y26 1 " "Info: 8: + IC(0.180 ns) + CELL(0.636 ns) = 3.163 ns; Loc. = LAB_X19_Y26; Fanout = 1; COMB Node = 'divider:inst4\|count~166'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "0.816 ns" { divider:inst4|add~202 divider:inst4|count~166 } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/divider.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.110 ns) 3.273 ns divider:inst4\|count\[5\] 9 REG LAB_X19_Y26 3 " "Info: 9: + IC(0.000 ns) + CELL(0.110 ns) = 3.273 ns; Loc. = LAB_X19_Y26; Fanout = 3; REG Node = 'divider:inst4\|count\[5\]'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "0.110 ns" { divider:inst4|count~166 divider:inst4|count[5] } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/divider.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.444 ns 74.67 % " "Info: Total cell delay = 2.444 ns ( 74.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.829 ns 25.33 % " "Info: Total interconnect delay = 0.829 ns ( 25.33 % )" {  } {  } 0}  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "3.273 ns" { divider:inst4|count[0] divider:inst4|add~193 divider:inst4|add~195 divider:inst4|add~197 divider:inst4|add~199 divider:inst4|add~201 divider:inst4|add~202 divider:inst4|count~166 divider:inst4|count[5] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Warning" "WDAT_PRELIMINARY_TIMING" "EP2C35F672C8 " "Warning: Timing characteristics of device EP2C35F672C8 are preliminary" {  } {  } 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "5 " "Warning: Found 5 output pins without output pin load capacitance assignment" { { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "key_down 0 " "Warning: Pin \"key_down\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "key_word\[3\] 0 " "Warning: Pin \"key_word\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "key_word\[2\] 0 " "Warning: Pin \"key_word\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "key_word\[1\] 0 " "Warning: Pin \"key_word\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "key_word\[0\] 0 " "Warning: Pin \"key_word\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0}  } {  } 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "5 " "Warning: Found 5 output pins without output pin load capacitance assignment" { { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "key_down 0 " "Warning: Pin \"key_down\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "key_word\[3\] 0 " "Warning: Pin \"key_word\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "key_word\[2\] 0 " "Warning: Pin \"key_word\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "key_word\[1\] 0 " "Warning: Pin \"key_word\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "key_word\[0\] 0 " "Warning: Pin \"key_word\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0}  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 13 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 23 12:19:02 2008 " "Info: Processing ended: Wed Apr 23 12:19:02 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0}  } {  } 0}