gewei.tan.qmsg

自己用VHDL写的键盘程序

{ "Info" "ITDB_TH_RESULT" "geweictrl:inst\|geweidcfq:inst\|q d clk 0.683 ns register " "Info: th for register \"geweictrl:inst\|geweidcfq:inst\|q\" (data pin = \"d\", clock pin = \"clk\") is 0.683 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.942 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "" { clk } "NODE_NAME" } "" } } { "gewei.bdf" "" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { -8 -24 144 8 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns clk~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "gewei.bdf" "" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { -8 -24 144 8 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.207 ns) + CELL(0.989 ns) 3.435 ns divider:inst4\|key_clock 3 REG LCFF_X19_Y26_N7 1 " "Info: 3: + IC(1.207 ns) + CELL(0.989 ns) = 3.435 ns; Loc. = LCFF_X19_Y26_N7; Fanout = 1; REG Node = 'divider:inst4\|key_clock'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "2.196 ns" { clk~clkctrl divider:inst4|key_clock } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/divider.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.567 ns) + CELL(0.000 ns) 6.002 ns divider:inst4\|key_clock~clkctrl 4 COMB CLKCTRL_G2 4 " "Info: 4: + IC(2.567 ns) + CELL(0.000 ns) = 6.002 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'divider:inst4\|key_clock~clkctrl'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "2.567 ns" { divider:inst4|key_clock divider:inst4|key_clock~clkctrl } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/divider.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.261 ns) + CELL(0.679 ns) 7.942 ns geweictrl:inst\|geweidcfq:inst\|q 5 REG LCFF_X27_Y1_N21 2 " "Info: 5: + IC(1.261 ns) + CELL(0.679 ns) = 7.942 ns; Loc. = LCFF_X27_Y1_N21; Fanout = 2; REG Node = 'geweictrl:inst\|geweidcfq:inst\|q'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "1.940 ns" { divider:inst4|key_clock~clkctrl geweictrl:inst|geweidcfq:inst|q } "NODE_NAME" } "" } } { "geweidcfq.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/geweidcfq.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.768 ns 34.85 % " "Info: Total cell delay = 2.768 ns ( 34.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.174 ns 65.15 % " "Info: Total interconnect delay = 5.174 ns ( 65.15 % )" {  } {  } 0}  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "7.942 ns" { clk clk~clkctrl divider:inst4|key_clock divider:inst4|key_clock~clkctrl geweictrl:inst|geweidcfq:inst|q } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.942 ns" { clk clk~combout clk~clkctrl divider:inst4|key_clock divider:inst4|key_clock~clkctrl geweictrl:inst|geweidcfq:inst|q } { 0.000ns 0.000ns 0.139ns 1.207ns 2.567ns 1.261ns } { 0.000ns 1.100ns 0.000ns 0.989ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.211 ns + " "Info: + Micro hold delay of destination is 0.211 ns" {  } { { "geweidcfq.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/geweidcfq.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.470 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.470 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns d 1 PIN PIN_AE13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_AE13; Fanout = 1; PIN Node = 'd'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "" { d } "NODE_NAME" } "" } } { "gewei.bdf" "" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { 128 -24 144 144 "d" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.067 ns) + CELL(0.469 ns) 7.470 ns geweictrl:inst\|geweidcfq:inst\|q 2 REG LCFF_X27_Y1_N21 2 " "Info: 2: + IC(6.067 ns) + CELL(0.469 ns) = 7.470 ns; Loc. = LCFF_X27_Y1_N21; Fanout = 2; REG Node = 'geweictrl:inst\|geweidcfq:inst\|q'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "6.536 ns" { d geweictrl:inst|geweidcfq:inst|q } "NODE_NAME" } "" } } { "geweidcfq.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/geweidcfq.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.403 ns 18.78 % " "Info: Total cell delay = 1.403 ns ( 18.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.067 ns 81.22 % " "Info: Total interconnect delay = 6.067 ns ( 81.22 % )" {  } {  } 0}  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "7.470 ns" { d geweictrl:inst|geweidcfq:inst|q } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.470 ns" { d d~combout geweictrl:inst|geweidcfq:inst|q } { 0.000ns 0.000ns 6.067ns } { 0.000ns 0.934ns 0.469ns } } }  } 0}  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "7.942 ns" { clk clk~clkctrl divider:inst4|key_clock divider:inst4|key_clock~clkctrl geweictrl:inst|geweidcfq:inst|q } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.942 ns" { clk clk~combout clk~clkctrl divider:inst4|key_clock divider:inst4|key_clock~clkctrl geweictrl:inst|geweidcfq:inst|q } { 0.000ns 0.000ns 0.139ns 1.207ns 2.567ns 1.261ns } { 0.000ns 1.100ns 0.000ns 0.989ns 0.000ns 0.679ns } } } { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "7.470 ns" { d geweictrl:inst|geweidcfq:inst|q } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.470 ns" { d d~combout geweictrl:inst|geweidcfq:inst|q } { 0.000ns 0.000ns 6.067ns } { 0.000ns 0.934ns 0.469ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 23 12:19:13 2008 " "Info: Processing ended: Wed Apr 23 12:19:13 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}