gewei.tan.qmsg

自己用VHDL写的键盘程序

{ "Info" "ITDB_TSU_RESULT" "geweictrl:inst\|geweidcfq:inst\|q d clk -0.512 ns register " "Info: tsu for register \"geweictrl:inst\|geweidcfq:inst\|q\" (data pin = \"d\", clock pin = \"clk\") is -0.512 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.470 ns + Longest pin register " "Info: + Longest pin to register delay is 7.470 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns d 1 PIN PIN_AE13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_AE13; Fanout = 1; PIN Node = 'd'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "" { d } "NODE_NAME" } "" } } { "gewei.bdf" "" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { 128 -24 144 144 "d" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.067 ns) + CELL(0.469 ns) 7.470 ns geweictrl:inst\|geweidcfq:inst\|q 2 REG LCFF_X27_Y1_N21 2 " "Info: 2: + IC(6.067 ns) + CELL(0.469 ns) = 7.470 ns; Loc. = LCFF_X27_Y1_N21; Fanout = 2; REG Node = 'geweictrl:inst\|geweidcfq:inst\|q'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "6.536 ns" { d geweictrl:inst|geweidcfq:inst|q } "NODE_NAME" } "" } } { "geweidcfq.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/geweidcfq.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.403 ns 18.78 % " "Info: Total cell delay = 1.403 ns ( 18.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.067 ns 81.22 % " "Info: Total interconnect delay = 6.067 ns ( 81.22 % )" {  } {  } 0}  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "7.470 ns" { d geweictrl:inst|geweidcfq:inst|q } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.470 ns" { d d~combout geweictrl:inst|geweidcfq:inst|q } { 0.000ns 0.000ns 6.067ns } { 0.000ns 0.934ns 0.469ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "geweidcfq.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/geweidcfq.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.942 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "" { clk } "NODE_NAME" } "" } } { "gewei.bdf" "" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { -8 -24 144 8 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns clk~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "gewei.bdf" "" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { -8 -24 144 8 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.207 ns) + CELL(0.989 ns) 3.435 ns divider:inst4\|key_clock 3 REG LCFF_X19_Y26_N7 1 " "Info: 3: + IC(1.207 ns) + CELL(0.989 ns) = 3.435 ns; Loc. = LCFF_X19_Y26_N7; Fanout = 1; REG Node = 'divider:inst4\|key_clock'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "2.196 ns" { clk~clkctrl divider:inst4|key_clock } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/divider.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.567 ns) + CELL(0.000 ns) 6.002 ns divider:inst4\|key_clock~clkctrl 4 COMB CLKCTRL_G2 4 " "Info: 4: + IC(2.567 ns) + CELL(0.000 ns) = 6.002 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'divider:inst4\|key_clock~clkctrl'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "2.567 ns" { divider:inst4|key_clock divider:inst4|key_clock~clkctrl } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/divider.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.261 ns) + CELL(0.679 ns) 7.942 ns geweictrl:inst\|geweidcfq:inst\|q 5 REG LCFF_X27_Y1_N21 2 " "Info: 5: + IC(1.261 ns) + CELL(0.679 ns) = 7.942 ns; Loc. = LCFF_X27_Y1_N21; Fanout = 2; REG Node = 'geweictrl:inst\|geweidcfq:inst\|q'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "1.940 ns" { divider:inst4|key_clock~clkctrl geweictrl:inst|geweidcfq:inst|q } "NODE_NAME" } "" } } { "geweidcfq.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/geweidcfq.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.768 ns 34.85 % " "Info: Total cell delay = 2.768 ns ( 34.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.174 ns 65.15 % " "Info: Total interconnect delay = 5.174 ns ( 65.15 % )" {  } {  } 0}  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "7.942 ns" { clk clk~clkctrl divider:inst4|key_clock divider:inst4|key_clock~clkctrl geweictrl:inst|geweidcfq:inst|q } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.942 ns" { clk clk~combout clk~clkctrl divider:inst4|key_clock divider:inst4|key_clock~clkctrl geweictrl:inst|geweidcfq:inst|q } { 0.000ns 0.000ns 0.139ns 1.207ns 2.567ns 1.261ns } { 0.000ns 1.100ns 0.000ns 0.989ns 0.000ns 0.679ns } } }  } 0}  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "7.470 ns" { d geweictrl:inst|geweidcfq:inst|q } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.470 ns" { d d~combout geweictrl:inst|geweidcfq:inst|q } { 0.000ns 0.000ns 6.067ns } { 0.000ns 0.934ns 0.469ns } } } { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "7.942 ns" { clk clk~clkctrl divider:inst4|key_clock divider:inst4|key_clock~clkctrl geweictrl:inst|geweidcfq:inst|q } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.942 ns" { clk clk~combout clk~clkctrl divider:inst4|key_clock divider:inst4|key_clock~clkctrl geweictrl:inst|geweidcfq:inst|q } { 0.000ns 0.000ns 0.139ns 1.207ns 2.567ns 1.261ns } { 0.000ns 1.100ns 0.000ns 0.989ns 0.000ns 0.679ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk key_word\[3\] geweictrl:inst\|geweidcfq:inst\|q 15.392 ns register " "Info: tco from clock \"clk\" to destination pin \"key_word\[3\]\" through register \"geweictrl:inst\|geweidcfq:inst\|q\" is 15.392 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.942 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "" { clk } "NODE_NAME" } "" } } { "gewei.bdf" "" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { -8 -24 144 8 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns clk~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "gewei.bdf" "" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { -8 -24 144 8 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.207 ns) + CELL(0.989 ns) 3.435 ns divider:inst4\|key_clock 3 REG LCFF_X19_Y26_N7 1 " "Info: 3: + IC(1.207 ns) + CELL(0.989 ns) = 3.435 ns; Loc. = LCFF_X19_Y26_N7; Fanout = 1; REG Node = 'divider:inst4\|key_clock'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "2.196 ns" { clk~clkctrl divider:inst4|key_clock } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/divider.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.567 ns) + CELL(0.000 ns) 6.002 ns divider:inst4\|key_clock~clkctrl 4 COMB CLKCTRL_G2 4 " "Info: 4: + IC(2.567 ns) + CELL(0.000 ns) = 6.002 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'divider:inst4\|key_clock~clkctrl'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "2.567 ns" { divider:inst4|key_clock divider:inst4|key_clock~clkctrl } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/divider.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.261 ns) + CELL(0.679 ns) 7.942 ns geweictrl:inst\|geweidcfq:inst\|q 5 REG LCFF_X27_Y1_N21 2 " "Info: 5: + IC(1.261 ns) + CELL(0.679 ns) = 7.942 ns; Loc. = LCFF_X27_Y1_N21; Fanout = 2; REG Node = 'geweictrl:inst\|geweidcfq:inst\|q'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "1.940 ns" { divider:inst4|key_clock~clkctrl geweictrl:inst|geweidcfq:inst|q } "NODE_NAME" } "" } } { "geweidcfq.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/geweidcfq.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.768 ns 34.85 % " "Info: Total cell delay = 2.768 ns ( 34.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.174 ns 65.15 % " "Info: Total interconnect delay = 5.174 ns ( 65.15 % )" {  } {  } 0}  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "7.942 ns" { clk clk~clkctrl divider:inst4|key_clock divider:inst4|key_clock~clkctrl geweictrl:inst|geweidcfq:inst|q } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.942 ns" { clk clk~combout clk~clkctrl divider:inst4|key_clock divider:inst4|key_clock~clkctrl geweictrl:inst|geweidcfq:inst|q } { 0.000ns 0.000ns 0.139ns 1.207ns 2.567ns 1.261ns } { 0.000ns 1.100ns 0.000ns 0.989ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns + " "Info: + Micro clock to output delay of source is 0.310 ns" {  } { { "geweidcfq.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/geweidcfq.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.140 ns + Longest register pin " "Info: + Longest register to pin delay is 7.140 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns geweictrl:inst\|geweidcfq:inst\|q 1 REG LCFF_X27_Y1_N21 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y1_N21; Fanout = 2; REG Node = 'geweictrl:inst\|geweidcfq:inst\|q'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "" { geweictrl:inst|geweidcfq:inst|q } "NODE_NAME" } "" } } { "geweidcfq.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/geweidcfq.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.468 ns) + CELL(0.664 ns) 1.132 ns geweictrl:inst\|inst4~24 2 COMB LCCOMB_X27_Y1_N26 5 " "Info: 2: + IC(0.468 ns) + CELL(0.664 ns) = 1.132 ns; Loc. = LCCOMB_X27_Y1_N26; Fanout = 5; COMB Node = 'geweictrl:inst\|inst4~24'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "1.132 ns" { geweictrl:inst|geweidcfq:inst|q geweictrl:inst|inst4~24 } "NODE_NAME" } "" } } { "geweictrl.bdf" "" { Schematic "E:/vhdl_exe/fpga论文/gewei/geweictrl.bdf" { { 216 576 640 296 "inst4" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.405 ns) + CELL(0.636 ns) 2.173 ns zd4:inst3\|key_word\[3\]~122 3 COMB LCCOMB_X27_Y1_N4 1 " "Info: 3: + IC(0.405 ns) + CELL(0.636 ns) = 2.173 ns; Loc. = LCCOMB_X27_Y1_N4; Fanout = 1; COMB Node = 'zd4:inst3\|key_word\[3\]~122'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "1.041 ns" { geweictrl:inst|inst4~24 zd4:inst3|key_word[3]~122 } "NODE_NAME" } "" } } { "zd4.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/zd4.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.880 ns) + CELL(3.087 ns) 7.140 ns key_word\[3\] 4 PIN PIN_AC14 0 " "Info: 4: + IC(1.880 ns) + CELL(3.087 ns) = 7.140 ns; Loc. = PIN_AC14; Fanout = 0; PIN Node = 'key_word\[3\]'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "4.967 ns" { zd4:inst3|key_word[3]~122 key_word[3] } "NODE_NAME" } "" } } { "gewei.bdf" "" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { 304 504 680 320 "key_word\[3..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.387 ns 61.44 % " "Info: Total cell delay = 4.387 ns ( 61.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.753 ns 38.56 % " "Info: Total interconnect delay = 2.753 ns ( 38.56 % )" {  } {  } 0}  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "7.140 ns" { geweictrl:inst|geweidcfq:inst|q geweictrl:inst|inst4~24 zd4:inst3|key_word[3]~122 key_word[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.140 ns" { geweictrl:inst|geweidcfq:inst|q geweictrl:inst|inst4~24 zd4:inst3|key_word[3]~122 key_word[3] } { 0.000ns 0.468ns 0.405ns 1.880ns } { 0.000ns 0.664ns 0.636ns 3.087ns } } }  } 0}  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "7.942 ns" { clk clk~clkctrl divider:inst4|key_clock divider:inst4|key_clock~clkctrl geweictrl:inst|geweidcfq:inst|q } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.942 ns" { clk clk~combout clk~clkctrl divider:inst4|key_clock divider:inst4|key_clock~clkctrl geweictrl:inst|geweidcfq:inst|q } { 0.000ns 0.000ns 0.139ns 1.207ns 2.567ns 1.261ns } { 0.000ns 1.100ns 0.000ns 0.989ns 0.000ns 0.679ns } } } { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "7.140 ns" { geweictrl:inst|geweidcfq:inst|q geweictrl:inst|inst4~24 zd4:inst3|key_word[3]~122 key_word[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.140 ns" { geweictrl:inst|geweidcfq:inst|q geweictrl:inst|inst4~24 zd4:inst3|key_word[3]~122 key_word[3] } { 0.000ns 0.468ns 0.405ns 1.880ns } { 0.000ns 0.664ns 0.636ns 3.087ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "key1 key_down 16.353 ns Longest " "Info: Longest tpd from source pin \"key1\" to destination pin \"key_down\" is 16.353 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns key1 1 PIN PIN_AA12 4 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_AA12; Fanout = 4; PIN Node = 'key1'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "" { key1 } "NODE_NAME" } "" } } { "gewei.bdf" "" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { 192 -24 144 208 "key1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.191 ns) + CELL(0.664 ns) 7.789 ns geweidecord:inst19\|reduce_or~2593 2 COMB LCCOMB_X25_Y1_N10 1 " "Info: 2: + IC(6.191 ns) + CELL(0.664 ns) = 7.789 ns; Loc. = LCCOMB_X25_Y1_N10; Fanout = 1; COMB Node = 'geweidecord:inst19\|reduce_or~2593'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "6.855 ns" { key1 geweidecord:inst19|reduce_or~2593 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.210 ns) 8.353 ns geweidecord:inst19\|reduce_or~2594 3 COMB LCCOMB_X25_Y1_N0 1 " "Info: 3: + IC(0.354 ns) + CELL(0.210 ns) = 8.353 ns; Loc. = LCCOMB_X25_Y1_N0; Fanout = 1; COMB Node = 'geweidecord:inst19\|reduce_or~2594'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "0.564 ns" { geweidecord:inst19|reduce_or~2593 geweidecord:inst19|reduce_or~2594 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.636 ns) 9.351 ns geweidecord:inst19\|reduce_or~2597 4 COMB LCCOMB_X25_Y1_N20 2 " "Info: 4: + IC(0.362 ns) + CELL(0.636 ns) = 9.351 ns; Loc. = LCCOMB_X25_Y1_N20; Fanout = 2; COMB Node = 'geweidecord:inst19\|reduce_or~2597'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "0.998 ns" { geweidecord:inst19|reduce_or~2594 geweidecord:inst19|reduce_or~2597 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.090 ns) + CELL(0.636 ns) 11.077 ns geweidecord:inst19\|bt 5 COMB LCCOMB_X27_Y1_N2 2 " "Info: 5: + IC(1.090 ns) + CELL(0.636 ns) = 11.077 ns; Loc. = LCCOMB_X27_Y1_N2; Fanout = 2; COMB Node = 'geweidecord:inst19\|bt'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "1.726 ns" { geweidecord:inst19|reduce_or~2597 geweidecord:inst19|bt } "NODE_NAME" } "" } } { "geweidecord.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/geweidecord.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.374 ns) + CELL(0.210 ns) 11.661 ns geweizd:inst2\|key_down~9 6 COMB LCCOMB_X27_Y1_N28 1 " "Info: 6: + IC(0.374 ns) + CELL(0.210 ns) = 11.661 ns; Loc. = LCCOMB_X27_Y1_N28; Fanout = 1; COMB Node = 'geweizd:inst2\|key_down~9'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "0.584 ns" { geweidecord:inst19|bt geweizd:inst2|key_down~9 } "NODE_NAME" } "" } } { "geweizd.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/geweizd.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.605 ns) + CELL(3.087 ns) 16.353 ns key_down 7 PIN PIN_AE9 0 " "Info: 7: + IC(1.605 ns) + CELL(3.087 ns) = 16.353 ns; Loc. = PIN_AE9; Fanout = 0; PIN Node = 'key_down'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "4.692 ns" { geweizd:inst2|key_down~9 key_down } "NODE_NAME" } "" } } { "gewei.bdf" "" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { 40 544 720 56 "key_down" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.377 ns 39.00 % " "Info: Total cell delay = 6.377 ns ( 39.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.976 ns 61.00 % " "Info: Total interconnect delay = 9.976 ns ( 61.00 % )" {  } {  } 0}  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "16.353 ns" { key1 geweidecord:inst19|reduce_or~2593 geweidecord:inst19|reduce_or~2594 geweidecord:inst19|reduce_or~2597 geweidecord:inst19|bt geweizd:inst2|key_down~9 key_down } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.353 ns" { key1 key1~combout geweidecord:inst19|reduce_or~2593 geweidecord:inst19|reduce_or~2594 geweidecord:inst19|reduce_or~2597 geweidecord:inst19|bt geweizd:inst2|key_down~9 key_down } { 0.000ns 0.000ns 6.191ns 0.354ns 0.362ns 1.090ns 0.374ns 1.605ns } { 0.000ns 0.934ns 0.664ns 0.210ns 0.636ns 0.636ns 0.210ns 3.087ns } } }  } 0}