gewei.tan.qmsg

自己用VHDL写的键盘程序

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "gewei.bdf" "" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { -8 -24 144 8 "clk" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "divider:inst4\|key_clock " "Info: Detected ripple clock \"divider:inst4\|key_clock\" as buffer" {  } { { "divider.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/divider.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "divider:inst4\|key_clock" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register divider:inst4\|div\[3\] register divider:inst4\|count\[1\] 251.76 MHz 3.972 ns Internal " "Info: Clock \"clk\" has Internal fmax of 251.76 MHz between source register \"divider:inst4\|div\[3\]\" and destination register \"divider:inst4\|count\[1\]\" (period= 3.972 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.702 ns + Longest register register " "Info: + Longest register to register delay is 3.702 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns divider:inst4\|div\[3\] 1 REG LCFF_X20_Y26_N17 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y26_N17; Fanout = 3; REG Node = 'divider:inst4\|div\[3\]'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "" { divider:inst4|div[3] } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/divider.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.771 ns) + CELL(0.664 ns) 1.435 ns divider:inst4\|reduce_nor~77 2 COMB LCCOMB_X19_Y26_N12 1 " "Info: 2: + IC(0.771 ns) + CELL(0.664 ns) = 1.435 ns; Loc. = LCCOMB_X19_Y26_N12; Fanout = 1; COMB Node = 'divider:inst4\|reduce_nor~77'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "1.435 ns" { divider:inst4|div[3] divider:inst4|reduce_nor~77 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.397 ns) + CELL(0.664 ns) 2.496 ns divider:inst4\|reduce_nor~0 3 COMB LCCOMB_X19_Y26_N14 9 " "Info: 3: + IC(0.397 ns) + CELL(0.664 ns) = 2.496 ns; Loc. = LCCOMB_X19_Y26_N14; Fanout = 9; COMB Node = 'divider:inst4\|reduce_nor~0'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "1.061 ns" { divider:inst4|reduce_nor~77 divider:inst4|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.334 ns) + CELL(0.872 ns) 3.702 ns divider:inst4\|count\[1\] 4 REG LCFF_X19_Y26_N19 3 " "Info: 4: + IC(0.334 ns) + CELL(0.872 ns) = 3.702 ns; Loc. = LCFF_X19_Y26_N19; Fanout = 3; REG Node = 'divider:inst4\|count\[1\]'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "1.206 ns" { divider:inst4|reduce_nor~0 divider:inst4|count[1] } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/divider.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 59.43 % " "Info: Total cell delay = 2.200 ns ( 59.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.502 ns 40.57 % " "Info: Total interconnect delay = 1.502 ns ( 40.57 % )" {  } {  } 0}  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "3.702 ns" { divider:inst4|div[3] divider:inst4|reduce_nor~77 divider:inst4|reduce_nor~0 divider:inst4|count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.702 ns" { divider:inst4|div[3] divider:inst4|reduce_nor~77 divider:inst4|reduce_nor~0 divider:inst4|count[1] } { 0.000ns 0.771ns 0.397ns 0.334ns } { 0.000ns 0.664ns 0.664ns 0.872ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.125 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.125 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "" { clk } "NODE_NAME" } "" } } { "gewei.bdf" "" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { -8 -24 144 8 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns clk~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "gewei.bdf" "" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { -8 -24 144 8 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.207 ns) + CELL(0.679 ns) 3.125 ns divider:inst4\|count\[1\] 3 REG LCFF_X19_Y26_N19 3 " "Info: 3: + IC(1.207 ns) + CELL(0.679 ns) = 3.125 ns; Loc. = LCFF_X19_Y26_N19; Fanout = 3; REG Node = 'divider:inst4\|count\[1\]'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "1.886 ns" { clk~clkctrl divider:inst4|count[1] } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/divider.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.779 ns 56.93 % " "Info: Total cell delay = 1.779 ns ( 56.93 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.346 ns 43.07 % " "Info: Total interconnect delay = 1.346 ns ( 43.07 % )" {  } {  } 0}  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "3.125 ns" { clk clk~clkctrl divider:inst4|count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.125 ns" { clk clk~combout clk~clkctrl divider:inst4|count[1] } { 0.000ns 0.000ns 0.139ns 1.207ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.125 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.125 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "" { clk } "NODE_NAME" } "" } } { "gewei.bdf" "" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { -8 -24 144 8 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns clk~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "gewei.bdf" "" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { -8 -24 144 8 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.207 ns) + CELL(0.679 ns) 3.125 ns divider:inst4\|div\[3\] 3 REG LCFF_X20_Y26_N17 3 " "Info: 3: + IC(1.207 ns) + CELL(0.679 ns) = 3.125 ns; Loc. = LCFF_X20_Y26_N17; Fanout = 3; REG Node = 'divider:inst4\|div\[3\]'" {  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "1.886 ns" { clk~clkctrl divider:inst4|div[3] } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/divider.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.779 ns 56.93 % " "Info: Total cell delay = 1.779 ns ( 56.93 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.346 ns 43.07 % " "Info: Total interconnect delay = 1.346 ns ( 43.07 % )" {  } {  } 0}  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "3.125 ns" { clk clk~clkctrl divider:inst4|div[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.125 ns" { clk clk~combout clk~clkctrl divider:inst4|div[3] } { 0.000ns 0.000ns 0.139ns 1.207ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0}  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "3.125 ns" { clk clk~clkctrl divider:inst4|count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.125 ns" { clk clk~combout clk~clkctrl divider:inst4|count[1] } { 0.000ns 0.000ns 0.139ns 1.207ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } } { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "3.125 ns" { clk clk~clkctrl divider:inst4|div[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.125 ns" { clk clk~combout clk~clkctrl divider:inst4|div[3] } { 0.000ns 0.000ns 0.139ns 1.207ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns + " "Info: + Micro clock to output delay of source is 0.310 ns" {  } { { "divider.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/divider.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "divider.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/divider.vhd" 10 -1 0 } }  } 0}  } { { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "3.702 ns" { divider:inst4|div[3] divider:inst4|reduce_nor~77 divider:inst4|reduce_nor~0 divider:inst4|count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.702 ns" { divider:inst4|div[3] divider:inst4|reduce_nor~77 divider:inst4|reduce_nor~0 divider:inst4|count[1] } { 0.000ns 0.771ns 0.397ns 0.334ns } { 0.000ns 0.664ns 0.664ns 0.872ns } } } { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "3.125 ns" { clk clk~clkctrl divider:inst4|count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.125 ns" { clk clk~combout clk~clkctrl divider:inst4|count[1] } { 0.000ns 0.000ns 0.139ns 1.207ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } } { "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" "" { Report "E:/vhdl_exe/fpga论文/gewei/db/gewei_cmp.qrpt" Compiler "gewei" "UNKNOWN" "V1" "E:/vhdl_exe/fpga论文/gewei/db/gewei.quartus_db" { Floorplan "E:/vhdl_exe/fpga论文/gewei/" "" "3.125 ns" { clk clk~clkctrl divider:inst4|div[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.125 ns" { clk clk~combout clk~clkctrl divider:inst4|div[3] } { 0.000ns 0.000ns 0.139ns 1.207ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0}