gewei.map.qmsg

自己用VHDL写的键盘程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 23 12:18:45 2008 " "Info: Processing started: Wed Apr 23 12:18:45 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off gewei -c gewei " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off gewei -c gewei" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../shiwei/dcfq.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../shiwei/dcfq.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dcfq-one " "Info: Found design unit 1: dcfq-one" {  } { { "../shiwei/dcfq.vhd" "" { Text "E:/vhdl_exe/fpga论文/shiwei/dcfq.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 dcfq " "Info: Found entity 1: dcfq" {  } { { "../shiwei/dcfq.vhd" "" { Text "E:/vhdl_exe/fpga论文/shiwei/dcfq.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../shiwei/ctrl.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../shiwei/ctrl.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ctrl " "Info: Found entity 1: ctrl" {  } { { "../shiwei/ctrl.bdf" "" { Schematic "E:/vhdl_exe/fpga论文/shiwei/ctrl.bdf" { } } }  } 0}  } {  } 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/vhdl_exe/fpga论文/gewei/dfq.vhd " "Warning: Can't analyze file -- file E:/vhdl_exe/fpga论文/gewei/dfq.vhd is missing" {  } {  } 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/vhdl_exe/fpga论文/gewei/ctrl.bdf " "Warning: Can't analyze file -- file E:/vhdl_exe/fpga论文/gewei/ctrl.bdf is missing" {  } {  } 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/vhdl_exe/fpga论文/gewei/dcfq.vhd " "Warning: Can't analyze file -- file E:/vhdl_exe/fpga论文/gewei/dcfq.vhd is missing" {  } {  } 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/vhdl_exe/fpga论文/gewei/zd.vhd " "Warning: Can't analyze file -- file E:/vhdl_exe/fpga论文/gewei/zd.vhd is missing" {  } {  } 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/vhdl_exe/fpga论文/gewei/decord.vhd " "Warning: Can't analyze file -- file E:/vhdl_exe/fpga论文/gewei/decord.vhd is missing" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "zd4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file zd4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 zd4-one " "Info: Found design unit 1: zd4-one" {  } { { "zd4.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/zd4.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 zd4 " "Info: Found entity 1: zd4" {  } { { "zd4.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/zd4.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gewei.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file gewei.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 gewei " "Info: Found entity 1: gewei" {  } { { "gewei.bdf" "" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "geweictrl.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file geweictrl.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 geweictrl " "Info: Found entity 1: geweictrl" {  } { { "geweictrl.bdf" "" { Schematic "E:/vhdl_exe/fpga论文/gewei/geweictrl.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "divider.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file divider.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divider-one " "Info: Found design unit 1: divider-one" {  } { { "divider.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/divider.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 divider " "Info: Found entity 1: divider" {  } { { "divider.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/divider.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "gewei " "Info: Elaborating entity \"gewei\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "out1 geweidecord inst19 " "Warning: Port \"out1\" of type geweidecord and instance \"inst19\" is missing source signal" {  } { { "gewei.bdf" "" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { 152 192 320 376 "inst19" "" } } } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "geweizd.vhd 2 1 " "Info: Using design file geweizd.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 geweizd-one " "Info: Found design unit 1: geweizd-one" {  } { { "geweizd.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/geweizd.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 geweizd " "Info: Found entity 1: geweizd" {  } { { "geweizd.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/geweizd.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "geweizd geweizd:inst2 " "Info: Elaborating entity \"geweizd\" for hierarchy \"geweizd:inst2\"" {  } { { "gewei.bdf" "inst2" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { 16 424 520 112 "inst2" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a geweizd.vhd(14) " "Warning: VHDL Process Statement warning at geweizd.vhd(14): signal \"a\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "geweizd.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/geweizd.vhd" 14 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "geweidecord.vhd 2 1 " "Info: Using design file geweidecord.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 geweidecord-one " "Info: Found design unit 1: geweidecord-one" {  } { { "geweidecord.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/geweidecord.vhd" 17 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 geweidecord " "Info: Found entity 1: geweidecord" {  } { { "geweidecord.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/geweidecord.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "geweidecord geweidecord:inst19 " "Info: Elaborating entity \"geweidecord\" for hierarchy \"geweidecord:inst19\"" {  } { { "gewei.bdf" "inst19" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { 152 192 320 376 "inst19" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "geweictrl geweictrl:inst " "Info: Elaborating entity \"geweictrl\" for hierarchy \"geweictrl:inst\"" {  } { { "gewei.bdf" "inst" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { 16 184 312 112 "inst" "" } } } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "geweidcfq.vhd 2 1 " "Info: Using design file geweidcfq.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 geweidcfq-one " "Info: Found design unit 1: geweidcfq-one" {  } { { "geweidcfq.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/geweidcfq.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 geweidcfq " "Info: Found entity 1: geweidcfq" {  } { { "geweidcfq.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/geweidcfq.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "geweidcfq geweictrl:inst\|geweidcfq:inst " "Info: Elaborating entity \"geweidcfq\" for hierarchy \"geweictrl:inst\|geweidcfq:inst\"" {  } { { "geweictrl.bdf" "inst" { Schematic "E:/vhdl_exe/fpga论文/gewei/geweictrl.bdf" { { 32 344 440 128 "inst" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "divider divider:inst4 " "Info: Elaborating entity \"divider\" for hierarchy \"divider:inst4\"" {  } { { "gewei.bdf" "inst4" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { 24 8 128 120 "inst4" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zd4 zd4:inst3 " "Info: Elaborating entity \"zd4\" for hierarchy \"zd4:inst3\"" {  } { { "gewei.bdf" "inst3" { Schematic "E:/vhdl_exe/fpga论文/gewei/gewei.bdf" { { 168 432 592 264 "inst3" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a zd4.vhd(14) " "Warning: VHDL Process Statement warning at zd4.vhd(14): signal \"a\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "zd4.vhd" "" { Text "E:/vhdl_exe/fpga论文/gewei/zd4.vhd" 14 0 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "81 " "Info: Implemented 81 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "64 " "Info: Implemented 64 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 23 12:18:49 2008 " "Info: Processing ended: Wed Apr 23 12:18:49 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}