gewei.tan.rpt

自己用VHDL写的键盘程序

+---------------------------------------------------------------------------------------------+
; th                                                                                          ;
+---------------+-------------+-----------+------+---------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                              ; To Clock ;
+---------------+-------------+-----------+------+---------------------------------+----------+
; N/A           ; None        ; 0.683 ns  ; d    ; geweictrl:inst|geweidcfq:inst|q ; clk      ;
+---------------+-------------+-----------+------+---------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Apr 23 12:19:13 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off gewei -c gewei --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "divider:inst4|key_clock" as buffer
Info: Clock "clk" has Internal fmax of 251.76 MHz between source register "divider:inst4|div[3]" and destination register "divider:inst4|count[1]" (period= 3.972 ns)
    Info: + Longest register to register delay is 3.702 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y26_N17; Fanout = 3; REG Node = 'divider:inst4|div[3]'
        Info: 2: + IC(0.771 ns) + CELL(0.664 ns) = 1.435 ns; Loc. = LCCOMB_X19_Y26_N12; Fanout = 1; COMB Node = 'divider:inst4|reduce_nor~77'
        Info: 3: + IC(0.397 ns) + CELL(0.664 ns) = 2.496 ns; Loc. = LCCOMB_X19_Y26_N14; Fanout = 9; COMB Node = 'divider:inst4|reduce_nor~0'
        Info: 4: + IC(0.334 ns) + CELL(0.872 ns) = 3.702 ns; Loc. = LCFF_X19_Y26_N19; Fanout = 3; REG Node = 'divider:inst4|count[1]'
        Info: Total cell delay = 2.200 ns ( 59.43 % )
        Info: Total interconnect delay = 1.502 ns ( 40.57 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.125 ns
            Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.207 ns) + CELL(0.679 ns) = 3.125 ns; Loc. = LCFF_X19_Y26_N19; Fanout = 3; REG Node = 'divider:inst4|count[1]'
            Info: Total cell delay = 1.779 ns ( 56.93 % )
            Info: Total interconnect delay = 1.346 ns ( 43.07 % )
        Info: - Longest clock path from clock "clk" to source register is 3.125 ns
            Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.207 ns) + CELL(0.679 ns) = 3.125 ns; Loc. = LCFF_X20_Y26_N17; Fanout = 3; REG Node = 'divider:inst4|div[3]'
            Info: Total cell delay = 1.779 ns ( 56.93 % )
            Info: Total interconnect delay = 1.346 ns ( 43.07 % )
    Info: + Micro clock to output delay of source is 0.310 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "geweictrl:inst|geweidcfq:inst|q" (data pin = "d", clock pin = "clk") is -0.512 ns
    Info: + Longest pin to register delay is 7.470 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_AE13; Fanout = 1; PIN Node = 'd'
        Info: 2: + IC(6.067 ns) + CELL(0.469 ns) = 7.470 ns; Loc. = LCFF_X27_Y1_N21; Fanout = 2; REG Node = 'geweictrl:inst|geweidcfq:inst|q'
        Info: Total cell delay = 1.403 ns ( 18.78 % )
        Info: Total interconnect delay = 6.067 ns ( 81.22 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 7.942 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.207 ns) + CELL(0.989 ns) = 3.435 ns; Loc. = LCFF_X19_Y26_N7; Fanout = 1; REG Node = 'divider:inst4|key_clock'
        Info: 4: + IC(2.567 ns) + CELL(0.000 ns) = 6.002 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'divider:inst4|key_clock~clkctrl'
        Info: 5: + IC(1.261 ns) + CELL(0.679 ns) = 7.942 ns; Loc. = LCFF_X27_Y1_N21; Fanout = 2; REG Node = 'geweictrl:inst|geweidcfq:inst|q'
        Info: Total cell delay = 2.768 ns ( 34.85 % )
        Info: Total interconnect delay = 5.174 ns ( 65.15 % )
Info: tco from clock "clk" to destination pin "key_word[3]" through register "geweictrl:inst|geweidcfq:inst|q" is 15.392 ns
    Info: + Longest clock path from clock "clk" to source register is 7.942 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.207 ns) + CELL(0.989 ns) = 3.435 ns; Loc. = LCFF_X19_Y26_N7; Fanout = 1; REG Node = 'divider:inst4|key_clock'
        Info: 4: + IC(2.567 ns) + CELL(0.000 ns) = 6.002 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'divider:inst4|key_clock~clkctrl'
        Info: 5: + IC(1.261 ns) + CELL(0.679 ns) = 7.942 ns; Loc. = LCFF_X27_Y1_N21; Fanout = 2; REG Node = 'geweictrl:inst|geweidcfq:inst|q'
        Info: Total cell delay = 2.768 ns ( 34.85 % )
        Info: Total interconnect delay = 5.174 ns ( 65.15 % )
    Info: + Micro clock to output delay of source is 0.310 ns
    Info: + Longest register to pin delay is 7.140 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y1_N21; Fanout = 2; REG Node = 'geweictrl:inst|geweidcfq:inst|q'
        Info: 2: + IC(0.468 ns) + CELL(0.664 ns) = 1.132 ns; Loc. = LCCOMB_X27_Y1_N26; Fanout = 5; COMB Node = 'geweictrl:inst|inst4~24'
        Info: 3: + IC(0.405 ns) + CELL(0.636 ns) = 2.173 ns; Loc. = LCCOMB_X27_Y1_N4; Fanout = 1; COMB Node = 'zd4:inst3|key_word[3]~122'
        Info: 4: + IC(1.880 ns) + CELL(3.087 ns) = 7.140 ns; Loc. = PIN_AC14; Fanout = 0; PIN Node = 'key_word[3]'
        Info: Total cell delay = 4.387 ns ( 61.44 % )
        Info: Total interconnect delay = 2.753 ns ( 38.56 % )
Info: Longest tpd from source pin "key1" to destination pin "key_down" is 16.353 ns
    Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_AA12; Fanout = 4; PIN Node = 'key1'
    Info: 2: + IC(6.191 ns) + CELL(0.664 ns) = 7.789 ns; Loc. = LCCOMB_X25_Y1_N10; Fanout = 1; COMB Node = 'geweidecord:inst19|reduce_or~2593'
    Info: 3: + IC(0.354 ns) + CELL(0.210 ns) = 8.353 ns; Loc. = LCCOMB_X25_Y1_N0; Fanout = 1; COMB Node = 'geweidecord:inst19|reduce_or~2594'
    Info: 4: + IC(0.362 ns) + CELL(0.636 ns) = 9.351 ns; Loc. = LCCOMB_X25_Y1_N20; Fanout = 2; COMB Node = 'geweidecord:inst19|reduce_or~2597'
    Info: 5: + IC(1.090 ns) + CELL(0.636 ns) = 11.077 ns; Loc. = LCCOMB_X27_Y1_N2; Fanout = 2; COMB Node = 'geweidecord:inst19|bt'
    Info: 6: + IC(0.374 ns) + CELL(0.210 ns) = 11.661 ns; Loc. = LCCOMB_X27_Y1_N28; Fanout = 1; COMB Node = 'geweizd:inst2|key_down~9'
    Info: 7: + IC(1.605 ns) + CELL(3.087 ns) = 16.353 ns; Loc. = PIN_AE9; Fanout = 0; PIN Node = 'key_down'
    Info: Total cell delay = 6.377 ns ( 39.00 % )
    Info: Total interconnect delay = 9.976 ns ( 61.00 % )
Info: th for register "geweictrl:inst|geweidcfq:inst|q" (data pin = "d", clock pin = "clk") is 0.683 ns
    Info: + Longest clock path from clock "clk" to destination register is 7.942 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.207 ns) + CELL(0.989 ns) = 3.435 ns; Loc. = LCFF_X19_Y26_N7; Fanout = 1; REG Node = 'divider:inst4|key_clock'
        Info: 4: + IC(2.567 ns) + CELL(0.000 ns) = 6.002 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'divider:inst4|key_clock~clkctrl'
        Info: 5: + IC(1.261 ns) + CELL(0.679 ns) = 7.942 ns; Loc. = LCFF_X27_Y1_N21; Fanout = 2; REG Node = 'geweictrl:inst|geweidcfq:inst|q'
        Info: Total cell delay = 2.768 ns ( 34.85 % )
        Info: Total interconnect delay = 5.174 ns ( 65.15 % )
    Info: + Micro hold delay of destination is 0.211 ns
    Info: - Shortest pin to register delay is 7.470 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_AE13; Fanout = 1; PIN Node = 'd'
        Info: 2: + IC(6.067 ns) + CELL(0.469 ns) = 7.470 ns; Loc. = LCFF_X27_Y1_N21; Fanout = 2; REG Node = 'geweictrl:inst|geweidcfq:inst|q'
        Info: Total cell delay = 1.403 ns ( 18.78 % )
        Info: Total interconnect delay = 6.067 ns ( 81.22 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Wed Apr 23 12:19:13 2008
    Info: Elapsed time: 00:00:00