sinout.tan.qmsg

基于MATLAB/DSP Ｂuild可控信号发生器

{ "Info" "ITDB_TH_RESULT" "SDelay:Delayi\|result\[7\] sclrp clock -9.722 ns register " "Info: th for register \"SDelay:Delayi\|result\[7\]\" (data pin = \"sclrp\", clock pin = \"clock\") is -9.722 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.111 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_28 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 14; CLK Node = 'clock'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "Sinout.vhd" "" { Text "E:/simulink/Sinout.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns SDelay:Delayi\|result\[7\] 2 REG LC_X45_Y9_N5 1 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X45_Y9_N5; Fanout = 1; REG Node = 'SDelay:Delayi\|result\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.642 ns" { clock SDelay:Delayi|result[7] } "NODE_NAME" } } { "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" 921 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 70.07 % ) " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns ( 29.93 % ) " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.111 ns" { clock SDelay:Delayi|result[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.111 ns" { clock clock~out0 SDelay:Delayi|result[7] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" 921 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.848 ns - Shortest pin register " "Info: - Shortest pin to register delay is 12.848 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns sclrp 1 PIN PIN_239 13 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_239; Fanout = 13; PIN Node = 'sclrp'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sclrp } "NODE_NAME" } } { "Sinout.vhd" "" { Text "E:/simulink/Sinout.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(10.895 ns) + CELL(0.478 ns) 12.848 ns SDelay:Delayi\|result\[7\] 2 REG LC_X45_Y9_N5 1 " "Info: 2: + IC(10.895 ns) + CELL(0.478 ns) = 12.848 ns; Loc. = LC_X45_Y9_N5; Fanout = 1; REG Node = 'SDelay:Delayi\|result\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.373 ns" { sclrp SDelay:Delayi|result[7] } "NODE_NAME" } } { "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" 921 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.953 ns ( 15.20 % ) " "Info: Total cell delay = 1.953 ns ( 15.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.895 ns ( 84.80 % ) " "Info: Total interconnect delay = 10.895 ns ( 84.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.848 ns" { sclrp SDelay:Delayi|result[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.848 ns" { sclrp sclrp~out0 SDelay:Delayi|result[7] } { 0.000ns 0.000ns 10.895ns } { 0.000ns 1.475ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.111 ns" { clock SDelay:Delayi|result[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.111 ns" { clock clock~out0 SDelay:Delayi|result[7] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.848 ns" { sclrp SDelay:Delayi|result[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.848 ns" { sclrp sclrp~out0 SDelay:Delayi|result[7] } { 0.000ns 0.000ns 10.895ns } { 0.000ns 1.475ns 0.478ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 31 10:01:31 2008 " "Info: Processing ended: Mon Mar 31 10:01:31 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}