sinout.tan.qmsg

基于MATLAB/DSP Ｂuild可控信号发生器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register IncDec:IncCounti\|counter\[0\] register SDelay:Delayi\|result\[1\] 252.08 MHz 3.967 ns Internal " "Info: Clock \"clock\" has Internal fmax of 252.08 MHz between source register \"IncDec:IncCounti\|counter\[0\]\" and destination register \"SDelay:Delayi\|result\[1\]\" (period= 3.967 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.706 ns + Longest register register " "Info: + Longest register to register delay is 3.706 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns IncDec:IncCounti\|counter\[0\] 1 REG LC_X44_Y9_N1 21 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X44_Y9_N1; Fanout = 21; REG Node = 'IncDec:IncCounti\|counter\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { IncDec:IncCounti|counter[0] } "NODE_NAME" } } { "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" 1578 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.854 ns) + CELL(0.590 ns) 1.444 ns SDelay:Delayi\|result~469 2 COMB LC_X43_Y9_N2 2 " "Info: 2: + IC(0.854 ns) + CELL(0.590 ns) = 1.444 ns; Loc. = LC_X43_Y9_N2; Fanout = 2; COMB Node = 'SDelay:Delayi\|result~469'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.444 ns" { IncDec:IncCounti|counter[0] SDelay:Delayi|result~469 } "NODE_NAME" } } { "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" 894 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.135 ns) + CELL(0.114 ns) 2.693 ns SDelay:Delayi\|result~473 3 COMB LC_X43_Y9_N5 1 " "Info: 3: + IC(1.135 ns) + CELL(0.114 ns) = 2.693 ns; Loc. = LC_X43_Y9_N5; Fanout = 1; COMB Node = 'SDelay:Delayi\|result~473'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.249 ns" { SDelay:Delayi|result~469 SDelay:Delayi|result~473 } "NODE_NAME" } } { "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" 894 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.406 ns) + CELL(0.607 ns) 3.706 ns SDelay:Delayi\|result\[1\] 4 REG LC_X43_Y9_N7 3 " "Info: 4: + IC(0.406 ns) + CELL(0.607 ns) = 3.706 ns; Loc. = LC_X43_Y9_N7; Fanout = 3; REG Node = 'SDelay:Delayi\|result\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.013 ns" { SDelay:Delayi|result~473 SDelay:Delayi|result[1] } "NODE_NAME" } } { "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" 921 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.311 ns ( 35.38 % ) " "Info: Total cell delay = 1.311 ns ( 35.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.395 ns ( 64.62 % ) " "Info: Total interconnect delay = 2.395 ns ( 64.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.706 ns" { IncDec:IncCounti|counter[0] SDelay:Delayi|result~469 SDelay:Delayi|result~473 SDelay:Delayi|result[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.706 ns" { IncDec:IncCounti|counter[0] SDelay:Delayi|result~469 SDelay:Delayi|result~473 SDelay:Delayi|result[1] } { 0.000ns 0.854ns 1.135ns 0.406ns } { 0.000ns 0.590ns 0.114ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.111 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_28 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 14; CLK Node = 'clock'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "Sinout.vhd" "" { Text "E:/simulink/Sinout.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns SDelay:Delayi\|result\[1\] 2 REG LC_X43_Y9_N7 3 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X43_Y9_N7; Fanout = 3; REG Node = 'SDelay:Delayi\|result\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.642 ns" { clock SDelay:Delayi|result[1] } "NODE_NAME" } } { "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" 921 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 70.07 % ) " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns ( 29.93 % ) " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.111 ns" { clock SDelay:Delayi|result[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.111 ns" { clock clock~out0 SDelay:Delayi|result[1] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.111 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_28 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 14; CLK Node = 'clock'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "Sinout.vhd" "" { Text "E:/simulink/Sinout.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns IncDec:IncCounti\|counter\[0\] 2 REG LC_X44_Y9_N1 21 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X44_Y9_N1; Fanout = 21; REG Node = 'IncDec:IncCounti\|counter\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.642 ns" { clock IncDec:IncCounti|counter[0] } "NODE_NAME" } } { "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" 1578 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 70.07 % ) " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns ( 29.93 % ) " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.111 ns" { clock IncDec:IncCounti|counter[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.111 ns" { clock clock~out0 IncDec:IncCounti|counter[0] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.111 ns" { clock SDelay:Delayi|result[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.111 ns" { clock clock~out0 SDelay:Delayi|result[1] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.111 ns" { clock IncDec:IncCounti|counter[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.111 ns" { clock clock~out0 IncDec:IncCounti|counter[0] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" 1578 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" 921 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.706 ns" { IncDec:IncCounti|counter[0] SDelay:Delayi|result~469 SDelay:Delayi|result~473 SDelay:Delayi|result[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.706 ns" { IncDec:IncCounti|counter[0] SDelay:Delayi|result~469 SDelay:Delayi|result~473 SDelay:Delayi|result[1] } { 0.000ns 0.854ns 1.135ns 0.406ns } { 0.000ns 0.590ns 0.114ns 0.607ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.111 ns" { clock SDelay:Delayi|result[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.111 ns" { clock clock~out0 SDelay:Delayi|result[1] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.111 ns" { clock IncDec:IncCounti|counter[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.111 ns" { clock clock~out0 IncDec:IncCounti|counter[0] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "SDelay:Delayi\|result\[4\] sclrp clock 11.831 ns register " "Info: tsu for register \"SDelay:Delayi\|result\[4\]\" (data pin = \"sclrp\", clock pin = \"clock\") is 11.831 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.905 ns + Longest pin register " "Info: + Longest pin to register delay is 14.905 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns sclrp 1 PIN PIN_239 13 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_239; Fanout = 13; PIN Node = 'sclrp'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sclrp } "NODE_NAME" } } { "Sinout.vhd" "" { Text "E:/simulink/Sinout.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(10.561 ns) + CELL(0.590 ns) 12.626 ns SDelay:Delayi\|result~471 2 COMB LC_X43_Y9_N6 6 " "Info: 2: + IC(10.561 ns) + CELL(0.590 ns) = 12.626 ns; Loc. = LC_X43_Y9_N6; Fanout = 6; COMB Node = 'SDelay:Delayi\|result~471'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.151 ns" { sclrp SDelay:Delayi|result~471 } "NODE_NAME" } } { "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" 894 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.106 ns) + CELL(0.442 ns) 14.174 ns SDelay:Delayi\|result~479 3 COMB LC_X42_Y9_N3 1 " "Info: 3: + IC(1.106 ns) + CELL(0.442 ns) = 14.174 ns; Loc. = LC_X42_Y9_N3; Fanout = 1; COMB Node = 'SDelay:Delayi\|result~479'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.548 ns" { SDelay:Delayi|result~471 SDelay:Delayi|result~479 } "NODE_NAME" } } { "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" 894 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.309 ns) 14.905 ns SDelay:Delayi\|result\[4\] 4 REG LC_X42_Y9_N1 2 " "Info: 4: + IC(0.422 ns) + CELL(0.309 ns) = 14.905 ns; Loc. = LC_X42_Y9_N1; Fanout = 2; REG Node = 'SDelay:Delayi\|result\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.731 ns" { SDelay:Delayi|result~479 SDelay:Delayi|result[4] } "NODE_NAME" } } { "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" 921 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.816 ns ( 18.89 % ) " "Info: Total cell delay = 2.816 ns ( 18.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.089 ns ( 81.11 % ) " "Info: Total interconnect delay = 12.089 ns ( 81.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.905 ns" { sclrp SDelay:Delayi|result~471 SDelay:Delayi|result~479 SDelay:Delayi|result[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "14.905 ns" { sclrp sclrp~out0 SDelay:Delayi|result~471 SDelay:Delayi|result~479 SDelay:Delayi|result[4] } { 0.000ns 0.000ns 10.561ns 1.106ns 0.422ns } { 0.000ns 1.475ns 0.590ns 0.442ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" 921 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.111 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_28 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 14; CLK Node = 'clock'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "Sinout.vhd" "" { Text "E:/simulink/Sinout.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns SDelay:Delayi\|result\[4\] 2 REG LC_X42_Y9_N1 2 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X42_Y9_N1; Fanout = 2; REG Node = 'SDelay:Delayi\|result\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.642 ns" { clock SDelay:Delayi|result[4] } "NODE_NAME" } } { "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" 921 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 70.07 % ) " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns ( 29.93 % ) " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.111 ns" { clock SDelay:Delayi|result[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.111 ns" { clock clock~out0 SDelay:Delayi|result[4] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.905 ns" { sclrp SDelay:Delayi|result~471 SDelay:Delayi|result~479 SDelay:Delayi|result[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "14.905 ns" { sclrp sclrp~out0 SDelay:Delayi|result~471 SDelay:Delayi|result~479 SDelay:Delayi|result[4] } { 0.000ns 0.000ns 10.561ns 1.106ns 0.422ns } { 0.000ns 1.475ns 0.590ns 0.442ns 0.309ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.111 ns" { clock SDelay:Delayi|result[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.111 ns" { clock clock~out0 SDelay:Delayi|result[4] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock oSinOuts\[0\] SDelay:Delayi\|result\[0\] 14.756 ns register " "Info: tco from clock \"clock\" to destination pin \"oSinOuts\[0\]\" through register \"SDelay:Delayi\|result\[0\]\" is 14.756 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.111 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_28 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 14; CLK Node = 'clock'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "Sinout.vhd" "" { Text "E:/simulink/Sinout.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns SDelay:Delayi\|result\[0\] 2 REG LC_X44_Y9_N9 1 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X44_Y9_N9; Fanout = 1; REG Node = 'SDelay:Delayi\|result\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.642 ns" { clock SDelay:Delayi|result[0] } "NODE_NAME" } } { "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" 921 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 70.07 % ) " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns ( 29.93 % ) " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.111 ns" { clock SDelay:Delayi|result[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.111 ns" { clock clock~out0 SDelay:Delayi|result[0] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" 921 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.421 ns + Longest register pin " "Info: + Longest register to pin delay is 11.421 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SDelay:Delayi\|result\[0\] 1 REG LC_X44_Y9_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X44_Y9_N9; Fanout = 1; REG Node = 'SDelay:Delayi\|result\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SDelay:Delayi|result[0] } "NODE_NAME" } } { "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD" 921 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.264 ns) + CELL(0.590 ns) 1.854 ns AltiMult:Product1i\|lpm_mult:Mult0\|multcore:mult_core\|_~15 2 COMB LC_X45_Y8_N9 3 " "Info: 2: + IC(1.264 ns) + CELL(0.590 ns) = 1.854 ns; Loc. = LC_X45_Y8_N9; Fanout = 3; COMB Node = 'AltiMult:Product1i\|lpm_mult:Mult0\|multcore:mult_core\|_~15'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.854 ns" { SDelay:Delayi|result[0] AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|_~15 } "NODE_NAME" } } { "lpm_mult.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_mult.tdf" 319 5 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.424 ns) + CELL(0.590 ns) 2.868 ns AltiMult:Product1i\|lpm_mult:Mult0\|multcore:mult_core\|lpm_add_sub:adder\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~61 3 COMB LC_X45_Y8_N0 1 " "Info: 3: + IC(0.424 ns) + CELL(0.590 ns) = 2.868 ns; Loc. = LC_X45_Y8_N0; Fanout = 1; COMB Node = 'AltiMult:Product1i\|lpm_mult:Mult0\|multcore:mult_core\|lpm_add_sub:adder\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~61'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.014 ns" { AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|_~15 AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~61 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.429 ns) + CELL(2.124 ns) 11.421 ns oSinOuts\[0\] 4 PIN PIN_21 0 " "Info: 4: + IC(6.429 ns) + CELL(2.124 ns) = 11.421 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'oSinOuts\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.553 ns" { AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~61 oSinOuts[0] } "NODE_NAME" } } { "Sinout.vhd" "" { Text "E:/simulink/Sinout.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.304 ns ( 28.93 % ) " "Info: Total cell delay = 3.304 ns ( 28.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.117 ns ( 71.07 % ) " "Info: Total interconnect delay = 8.117 ns ( 71.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.421 ns" { SDelay:Delayi|result[0] AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|_~15 AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~61 oSinOuts[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.421 ns" { SDelay:Delayi|result[0] AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|_~15 AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~61 oSinOuts[0] } { 0.000ns 1.264ns 0.424ns 6.429ns } { 0.000ns 0.590ns 0.590ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.111 ns" { clock SDelay:Delayi|result[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.111 ns" { clock clock~out0 SDelay:Delayi|result[0] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.421 ns" { SDelay:Delayi|result[0] AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|_~15 AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~61 oSinOuts[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.421 ns" { SDelay:Delayi|result[0] AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|_~15 AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~61 oSinOuts[0] } { 0.000ns 1.264ns 0.424ns 6.429ns } { 0.000ns 0.590ns 0.590ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "iSinctrls oSinOuts\[0\] 22.334 ns Longest " "Info: Longest tpd from source pin \"iSinctrls\" to destination pin \"oSinOuts\[0\]\" is 22.334 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns iSinctrls 1 PIN PIN_240 22 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_240; Fanout = 22; PIN Node = 'iSinctrls'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { iSinctrls } "NODE_NAME" } } { "Sinout.vhd" "" { Text "E:/simulink/Sinout.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(11.000 ns) + CELL(0.292 ns) 12.767 ns AltiMult:Product1i\|lpm_mult:Mult0\|multcore:mult_core\|_~15 2 COMB LC_X45_Y8_N9 3 " "Info: 2: + IC(11.000 ns) + CELL(0.292 ns) = 12.767 ns; Loc. = LC_X45_Y8_N9; Fanout = 3; COMB Node = 'AltiMult:Product1i\|lpm_mult:Mult0\|multcore:mult_core\|_~15'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.292 ns" { iSinctrls AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|_~15 } "NODE_NAME" } } { "lpm_mult.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_mult.tdf" 319 5 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.424 ns) + CELL(0.590 ns) 13.781 ns AltiMult:Product1i\|lpm_mult:Mult0\|multcore:mult_core\|lpm_add_sub:adder\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~61 3 COMB LC_X45_Y8_N0 1 " "Info: 3: + IC(0.424 ns) + CELL(0.590 ns) = 13.781 ns; Loc. = LC_X45_Y8_N0; Fanout = 1; COMB Node = 'AltiMult:Product1i\|lpm_mult:Mult0\|multcore:mult_core\|lpm_add_sub:adder\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~61'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.014 ns" { AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|_~15 AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~61 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.429 ns) + CELL(2.124 ns) 22.334 ns oSinOuts\[0\] 4 PIN PIN_21 0 " "Info: 4: + IC(6.429 ns) + CELL(2.124 ns) = 22.334 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'oSinOuts\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.553 ns" { AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~61 oSinOuts[0] } "NODE_NAME" } } { "Sinout.vhd" "" { Text "E:/simulink/Sinout.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.481 ns ( 20.06 % ) " "Info: Total cell delay = 4.481 ns ( 20.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "17.853 ns ( 79.94 % ) " "Info: Total interconnect delay = 17.853 ns ( 79.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "22.334 ns" { iSinctrls AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|_~15 AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~61 oSinOuts[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "22.334 ns" { iSinctrls iSinctrls~out0 AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|_~15 AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~61 oSinOuts[0] } { 0.000ns 0.000ns 11.000ns 0.424ns 6.429ns } { 0.000ns 1.475ns 0.292ns 0.590ns 2.124ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}