📄 sinout_dspbuilder_report.html
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<title>DSP Builder Report File</title>
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<h3>DSP Builder Report File for Sinout.mdl</h3>
<hr><h3>Project Setting</h3><TABLE>
<TR>
<TD><b>Device Family</b> </TD> <TD>Cyclone</TD>
</TR>
<TR>
<TD><b>Synthesis Tool</b> </TD> <TD>Quartus II</TD>
</TR>
<TR>
<TD> <b>Optimization </b></TD> <TD>Speed</TD>
</TR>
<TR>
<TD> <b>Date</b> </TD> <TD>Monday, March 31, 2008</TD>
</TR>
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<TD> <b>Time</b> </TD> <TD>10:01:08</TD>
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<TD><b>Version</b> </TD> <TD> 2.1.3 Build 31</TD>
</TR>
</TABLE>
<hr>
<h3>Compilation </h3>
<TABLE>
<TR>
<TD>Convert Mdl to VHDL </TD> <TD><b>:</b> PASSED </TD><TD></TD>
</TR>
<TR>
<TD>Synthesis </TD> <TD><b>:</b> --------- </TD><TD></TD>
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<TD>Quartus II Fitter</TD> <TD><b>:</b> --------- </TD><TD></TD>
</TR>
</TABLE>
<hr>
<!--<h3>Resource Utilization</h3>-->
<!--<h3>Timing Information</h3>-->
<h3>Input Output Pin Information</h3><TABLE>
<TR><TD><b>Pin name </b></TD>
<TD><b>Pin Direction </b></TD>
<TD><b>Bus Type </b></TD></TR>
<TR><TD> clock </TD><TD> in </TD><TD>std_logic</TD></TR><TR><TD> sclrp </TD><TD> in </TD><TD>std_logic</TD></TR><TR><TD> iSinctrls </TD><TD> in </TD><TD>std_logic</TD></TR><TR><TD> oSinOuts </TD><TD> out </TD><TD>std_logic_vector(7 downto 0)</TD></TR><TR><TD></TR></TABLE><br>
<p><b>Clock input pin :</b> All registered blocks use the input clock signal <b>'clock'</b>. Sinout.mdl does not use PLL.<br><b>Reset input pin :</b> All registered blocks use the global reset input signal <b>'sclrp'</b> , which is synchronous and active high</p><hr>
<h3>Files Generated by SignalCompiler</h3><TABLE BORDER>
<TR>
<TD> <b>Sinout.vhd</b> </TD><TD>VHDL representation of the design for synthesis and simulation </TD>
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<TD> <b>Sinout_quartus.tcl</b> </TD><TD>Tcl script for Quartus<font size="-1"><sup>®</font></sup> II compilation. <p><I>When compiling the design manually in the Quartus II software, type </i><b>source Sinout_quartus.tcl </b><i> in the Quartus II tcl console (Auxiliary Windows). The Quartus II software executes the Tcl script that sets up the project and environment for your design.</I></p></TD>
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<TD> <b>Sinout.vec</b> </TD><TD>Quartus<font size="-1"><sup>®</font></sup> II simulation vector file </TD>
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<TD><b> tb_Sinout.vhd</b> </TD><TD>VHDL design testbench for simulation </TD>
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<TD> <b>tb_Sinout.tcl</b> </TD><TD>Tcl script for ModelSim simulation <p><I>type </i><b>do tb_Sinout.tcl </b><i> at Modelsim prompt.</p></TD>
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<TD><b> tb_Sinout.v</b> </TD><TD>Verilog design testbench for simulation with Quartus II Verilog Output File (.vo)</TD>
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<TD> <b>DSPBuilder_Sinout\class.ptf</b> </TD><TD>PTF Configuration file to import the Simulink design 'Sinout' in SOPC Builder as an Avalon peripheral</TD>
</TR>
</TABLE><br>
<hr>
<h3>Synthesis & Compilation Log Files</h3>
<!--<p><A HREF="Sinout.srr">Synplicity Log</A></p>-->
<!--<p><A HREF="exemplar.log">Leonardo Log</A></p>-->
<!--<p><A HREF="Sinout.map.rpt">Quartus II Map Log</A></p>-->
<!--<p><A HREF="Sinout.fit.rpt">Quartus II Fit Log</A></p>-->
<hr>
<h3>Entity Sinout</h3>
<p><A HREF="DSPBuilder_Sinout\SinoutblockInfos.html">Information page</A> on the DSP Builder blocks used in Sinout.</p>
<h4>Warning Section</h4><p>
<b> Signals Out of Range </b>: This section lists the signals with a bit width greater than 51 bits. Fixed-point DSP Builder models support up to 51 bits of resolution. When the bit width grows over 51 bits, additional VHDL RTL simulations are recommended to estimate the effect of overflow and rounding introduced by double signals.</p><pre>
</pre>
<hr>
<h3>SOPC Builder section</h3>
<h4>Class.ptf Configuration file</h4>
<p>
DSPBuilder_Sinout\class.ptf is the PTF Configuration file to import the Simulink design 'Sinout' in SOPC Builder as an Avalon peripheral
</p>
<p>To use this file in SOPC Builder :</p><TABLE>
<TR>
<TD><b> - </b> </TD> <TD>Start SOPC Builder from the directory E:\simulink</TD>
</TR>
<TR>
<TD> <b> - </b></TD> <TD>The DSP Builder design 'Sinout' is listed as a peripheral in the SOPC Builder browser</TD>
</TR>
</TABLE><br>
<hr>
<TABLE><TR><TD align="left"><A HREF="http://www.altera.com/">wwww.altera.com</A></TD>
<TD> </TD><TD align="right"> <A HREF="C:\altera\DSPBuilder\Altlib\..\doc\dsp_builder_ugTOC.html">help</A></TD>
</TR></TABLE><hr>
DSP Builder <br>Quartus II development tool and MATLAB/Simulink Interface
<br>Version 2.1.3 Build 31<p>Copyright © 2001-2003 Altera Corporation. All rights reserved.</p>
<p>The DSP Builder software, including, without limitation, the clock-cycle limited
versions of the MegaCore® Logic Functions included therein, may only be used to
develop designs for programmable logic devices manufactured by Altera Corporation
and sold by Altera Corporation and its authorized distributors. IN NO EVENT MAY
SUCH SOFTWARE AND FUNCTIONS BE USED TO PROGRAM ANY PROGRAMMABLE LOGIC DEVICES, FIELD
PROGRAMMABLE GATE ARRAYS, ASICS, STANDARD PRODUCTS, OR ANY OTHER SEMICONDUCTOR
DEVICE MANUFACTURED BY ANY COMPANY OR ENTITY OTHER THAN ALTERA. For the complete
terms and conditions applicable to your use of the software and functions, please
refer to the Altera Program License.</p>
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