sinout.tan.rpt

基于MATLAB/DSP Ｂuild可控信号发生器

+-------+-------------------+-----------------+-----------+-------------+
; N/A   ; None              ; 22.334 ns       ; iSinctrls ; oSinOuts[0] ;
; N/A   ; None              ; 21.816 ns       ; iSinctrls ; oSinOuts[1] ;
; N/A   ; None              ; 19.149 ns       ; iSinctrls ; oSinOuts[2] ;
; N/A   ; None              ; 19.088 ns       ; iSinctrls ; oSinOuts[6] ;
; N/A   ; None              ; 19.072 ns       ; iSinctrls ; oSinOuts[5] ;
; N/A   ; None              ; 19.062 ns       ; iSinctrls ; oSinOuts[7] ;
; N/A   ; None              ; 18.893 ns       ; iSinctrls ; oSinOuts[4] ;
; N/A   ; None              ; 18.811 ns       ; iSinctrls ; oSinOuts[3] ;
+-------+-------------------+-----------------+-----------+-------------+


+-------------------------------------------------------------------------------------------+
; th                                                                                        ;
+---------------+-------------+------------+-------+-----------------------------+----------+
; Minimum Slack ; Required th ; Actual th  ; From  ; To                          ; To Clock ;
+---------------+-------------+------------+-------+-----------------------------+----------+
; N/A           ; None        ; -9.722 ns  ; sclrp ; SDelay:Delayi|result[7]     ; clock    ;
; N/A           ; None        ; -9.814 ns  ; sclrp ; SDelay:Delayi|result[0]     ; clock    ;
; N/A           ; None        ; -10.391 ns ; sclrp ; IncDec:IncCounti|counter[5] ; clock    ;
; N/A           ; None        ; -10.391 ns ; sclrp ; IncDec:IncCounti|counter[4] ; clock    ;
; N/A           ; None        ; -10.391 ns ; sclrp ; IncDec:IncCounti|counter[3] ; clock    ;
; N/A           ; None        ; -10.391 ns ; sclrp ; IncDec:IncCounti|counter[2] ; clock    ;
; N/A           ; None        ; -10.391 ns ; sclrp ; IncDec:IncCounti|counter[1] ; clock    ;
; N/A           ; None        ; -10.391 ns ; sclrp ; IncDec:IncCounti|counter[0] ; clock    ;
; N/A           ; None        ; -10.613 ns ; sclrp ; SDelay:Delayi|result[3]     ; clock    ;
; N/A           ; None        ; -10.615 ns ; sclrp ; SDelay:Delayi|result[6]     ; clock    ;
; N/A           ; None        ; -11.146 ns ; sclrp ; SDelay:Delayi|result[1]     ; clock    ;
; N/A           ; None        ; -11.149 ns ; sclrp ; SDelay:Delayi|result[2]     ; clock    ;
; N/A           ; None        ; -11.330 ns ; sclrp ; SDelay:Delayi|result[5]     ; clock    ;
; N/A           ; None        ; -11.352 ns ; sclrp ; SDelay:Delayi|result[4]     ; clock    ;
+---------------+-------------+------------+-------+-----------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Mar 31 10:01:31 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Sinout -c Sinout --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" has Internal fmax of 252.08 MHz between source register "IncDec:IncCounti|counter[0]" and destination register "SDelay:Delayi|result[1]" (period= 3.967 ns)
    Info: + Longest register to register delay is 3.706 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X44_Y9_N1; Fanout = 21; REG Node = 'IncDec:IncCounti|counter[0]'
        Info: 2: + IC(0.854 ns) + CELL(0.590 ns) = 1.444 ns; Loc. = LC_X43_Y9_N2; Fanout = 2; COMB Node = 'SDelay:Delayi|result~469'
        Info: 3: + IC(1.135 ns) + CELL(0.114 ns) = 2.693 ns; Loc. = LC_X43_Y9_N5; Fanout = 1; COMB Node = 'SDelay:Delayi|result~473'
        Info: 4: + IC(0.406 ns) + CELL(0.607 ns) = 3.706 ns; Loc. = LC_X43_Y9_N7; Fanout = 3; REG Node = 'SDelay:Delayi|result[1]'
        Info: Total cell delay = 1.311 ns ( 35.38 % )
        Info: Total interconnect delay = 2.395 ns ( 64.62 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clock" to destination register is 3.111 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 14; CLK Node = 'clock'
            Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X43_Y9_N7; Fanout = 3; REG Node = 'SDelay:Delayi|result[1]'
            Info: Total cell delay = 2.180 ns ( 70.07 % )
            Info: Total interconnect delay = 0.931 ns ( 29.93 % )
        Info: - Longest clock path from clock "clock" to source register is 3.111 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 14; CLK Node = 'clock'
            Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X44_Y9_N1; Fanout = 21; REG Node = 'IncDec:IncCounti|counter[0]'
            Info: Total cell delay = 2.180 ns ( 70.07 % )
            Info: Total interconnect delay = 0.931 ns ( 29.93 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "SDelay:Delayi|result[4]" (data pin = "sclrp", clock pin = "clock") is 11.831 ns
    Info: + Longest pin to register delay is 14.905 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_239; Fanout = 13; PIN Node = 'sclrp'
        Info: 2: + IC(10.561 ns) + CELL(0.590 ns) = 12.626 ns; Loc. = LC_X43_Y9_N6; Fanout = 6; COMB Node = 'SDelay:Delayi|result~471'
        Info: 3: + IC(1.106 ns) + CELL(0.442 ns) = 14.174 ns; Loc. = LC_X42_Y9_N3; Fanout = 1; COMB Node = 'SDelay:Delayi|result~479'
        Info: 4: + IC(0.422 ns) + CELL(0.309 ns) = 14.905 ns; Loc. = LC_X42_Y9_N1; Fanout = 2; REG Node = 'SDelay:Delayi|result[4]'
        Info: Total cell delay = 2.816 ns ( 18.89 % )
        Info: Total interconnect delay = 12.089 ns ( 81.11 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clock" to destination register is 3.111 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 14; CLK Node = 'clock'
        Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X42_Y9_N1; Fanout = 2; REG Node = 'SDelay:Delayi|result[4]'
        Info: Total cell delay = 2.180 ns ( 70.07 % )
        Info: Total interconnect delay = 0.931 ns ( 29.93 % )
Info: tco from clock "clock" to destination pin "oSinOuts[0]" through register "SDelay:Delayi|result[0]" is 14.756 ns
    Info: + Longest clock path from clock "clock" to source register is 3.111 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 14; CLK Node = 'clock'
        Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X44_Y9_N9; Fanout = 1; REG Node = 'SDelay:Delayi|result[0]'
        Info: Total cell delay = 2.180 ns ( 70.07 % )
        Info: Total interconnect delay = 0.931 ns ( 29.93 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 11.421 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X44_Y9_N9; Fanout = 1; REG Node = 'SDelay:Delayi|result[0]'
        Info: 2: + IC(1.264 ns) + CELL(0.590 ns) = 1.854 ns; Loc. = LC_X45_Y8_N9; Fanout = 3; COMB Node = 'AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|_~15'
        Info: 3: + IC(0.424 ns) + CELL(0.590 ns) = 2.868 ns; Loc. = LC_X45_Y8_N0; Fanout = 1; COMB Node = 'AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~61'
        Info: 4: + IC(6.429 ns) + CELL(2.124 ns) = 11.421 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'oSinOuts[0]'
        Info: Total cell delay = 3.304 ns ( 28.93 % )
        Info: Total interconnect delay = 8.117 ns ( 71.07 % )
Info: Longest tpd from source pin "iSinctrls" to destination pin "oSinOuts[0]" is 22.334 ns
    Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_240; Fanout = 22; PIN Node = 'iSinctrls'
    Info: 2: + IC(11.000 ns) + CELL(0.292 ns) = 12.767 ns; Loc. = LC_X45_Y8_N9; Fanout = 3; COMB Node = 'AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|_~15'
    Info: 3: + IC(0.424 ns) + CELL(0.590 ns) = 13.781 ns; Loc. = LC_X45_Y8_N0; Fanout = 1; COMB Node = 'AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~61'
    Info: 4: + IC(6.429 ns) + CELL(2.124 ns) = 22.334 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'oSinOuts[0]'
    Info: Total cell delay = 4.481 ns ( 20.06 % )
    Info: Total interconnect delay = 17.853 ns ( 79.94 % )
Info: th for register "SDelay:Delayi|result[7]" (data pin = "sclrp", clock pin = "clock") is -9.722 ns
    Info: + Longest clock path from clock "clock" to destination register is 3.111 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 14; CLK Node = 'clock'
        Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X45_Y9_N5; Fanout = 1; REG Node = 'SDelay:Delayi|result[7]'
        Info: Total cell delay = 2.180 ns ( 70.07 % )
        Info: Total interconnect delay = 0.931 ns ( 29.93 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 12.848 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_239; Fanout = 13; PIN Node = 'sclrp'
        Info: 2: + IC(10.895 ns) + CELL(0.478 ns) = 12.848 ns; Loc. = LC_X45_Y9_N5; Fanout = 1; REG Node = 'SDelay:Delayi|result[7]'
        Info: Total cell delay = 1.953 ns ( 15.20 % )
        Info: Total interconnect delay = 10.895 ns ( 84.80 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Mar 31 10:01:31 2008
    Info: Elapsed time: 00:00:01