sinout.vqm

基于MATLAB/DSP Ｂuild可控信号发生器

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version"

// DATE "03/31/2008 10:01:33"

module 	Sinout (
	clock,
	sclrp,
	iSinctrls,
	oSinOuts);
input 	clock;
input 	sclrp;
input 	iSinctrls;
output 	[7:0] oSinOuts;
wire \IncDec:IncCounti|counter[0] ;
wire \IncDec:IncCounti|counter[0]~65 ;
wire \IncDec:IncCounti|counter[0]~65COUT1_68 ;
wire \IncDec:IncCounti|counter[1] ;
wire \IncDec:IncCounti|counter[1]~61 ;
wire \IncDec:IncCounti|counter[1]~61COUT1_69 ;
wire \IncDec:IncCounti|counter[2] ;
wire \IncDec:IncCounti|counter[2]~62 ;
wire \IncDec:IncCounti|counter[2]~62COUT1 ;
wire \IncDec:IncCounti|counter[3] ;
wire \IncDec:IncCounti|counter[3]~66 ;
wire \IncDec:IncCounti|counter[4] ;
wire \IncDec:IncCounti|counter[4]~64 ;
wire \IncDec:IncCounti|counter[4]~64COUT1_70 ;
wire \IncDec:IncCounti|counter[5] ;
wire \SDelay:Delayi|result~464 ;
wire \SDelay:Delayi|result~465 ;
wire \SDelay:Delayi|result~463 ;
wire \SDelay:Delayi|result[0] ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|_~15 ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~61 ;
wire \SDelay:Delayi|result~469 ;
wire \SDelay:Delayi|result~471 ;
wire \SDelay:Delayi|result~470 ;
wire \SDelay:Delayi|result~472 ;
wire \SDelay:Delayi|result~473 ;
wire \SDelay:Delayi|result~467 ;
wire \SDelay:Delayi|result~468 ;
wire \SDelay:Delayi|result[1] ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~62 ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~62COUT1_78 ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~63 ;
wire \Mux5~147 ;
wire \Mux5~148 ;
wire \SDelay:Delayi|result~475 ;
wire \Mux5~149 ;
wire \SDelay:Delayi|result[2] ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~64 ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~64COUT1_79 ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~65 ;
wire \Mux4~149 ;
wire \Mux4~148 ;
wire \Mux4~147 ;
wire \SDelay:Delayi|result~477 ;
wire \SDelay:Delayi|result[3] ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~66 ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~66COUT1_80 ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~67 ;
wire \Mux3~149 ;
wire \Mux3~148 ;
wire \Mux3~147 ;
wire \SDelay:Delayi|result~479 ;
wire \SDelay:Delayi|result[4] ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~68 ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~68COUT1 ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~69 ;
wire \Mux2~149 ;
wire \Mux2~147 ;
wire \Mux2~148 ;
wire \SDelay:Delayi|result~481 ;
wire \SDelay:Delayi|result[5] ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~70 ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~71 ;
wire \Mux1~157 ;
wire \Mux1~156 ;
wire \SDelay:Delayi|result~484 ;
wire \SDelay:Delayi|result~483 ;
wire \SDelay:Delayi|result[6] ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~72 ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~72COUT1_81 ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~73 ;
wire \SDelay:Delayi|result~486 ;
wire \SDelay:Delayi|result[7] ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~74 ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~74COUT1_82 ;
wire \AltiMult:Product1i|lpm_mult:Mult0|multcore:mult_core|lpm_add_sub:adder|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~75 ;
wire [5:0] \IncDec:IncCounti|counter ;
wire [8:0] \SDelay:Delayi|result ;


wire gnd;
wire vcc;

assign gnd = 1'b0;
assign vcc = 1'b1;


cyclone_lcell \IncDec:IncCounti|counter[0]~I (
	.clk(clock),
	.dataa(\IncDec:IncCounti|counter[0] ),
	.aclr(gnd),
	.sclr(sclrp),
	.regout(\IncDec:IncCounti|counter[0] ),
	.cout(\IncDec:IncCounti|counter[0]~65 ));
defparam \IncDec:IncCounti|counter[0]~I .operation_mode = "arithmetic";
defparam \IncDec:IncCounti|counter[0]~I .synch_mode = "on";
defparam \IncDec:IncCounti|counter[0]~I .register_cascade_mode = "off";
defparam \IncDec:IncCounti|counter[0]~I .sum_lutc_input = "datac";
defparam \IncDec:IncCounti|counter[0]~I .lut_mask = "55AA";
defparam \IncDec:IncCounti|counter[0]~I .output_mode = "reg_only";

cyclone_lcell \IncDec:IncCounti|counter[1]~I (
	.clk(clock),
	.dataa(\IncDec:IncCounti|counter[1] ),
	.aclr(gnd),
	.sclr(sclrp),
	.cin(\IncDec:IncCounti|counter[0]~65 ),
	.regout(\IncDec:IncCounti|counter[1] ),
	.cout(\IncDec:IncCounti|counter[1]~61 ));
defparam \IncDec:IncCounti|counter[1]~I .operation_mode = "arithmetic";
defparam \IncDec:IncCounti|counter[1]~I .synch_mode = "on";
defparam \IncDec:IncCounti|counter[1]~I .register_cascade_mode = "off";
defparam \IncDec:IncCounti|counter[1]~I .sum_lutc_input = "cin";
defparam \IncDec:IncCounti|counter[1]~I .lut_mask = "5A5F";
defparam \IncDec:IncCounti|counter[1]~I .output_mode = "reg_only";

cyclone_lcell \IncDec:IncCounti|counter[2]~I (
	.clk(clock),
	.datab(\IncDec:IncCounti|counter[2] ),
	.aclr(gnd),
	.sclr(sclrp),
	.cin(\IncDec:IncCounti|counter[1]~61 ),
	.regout(\IncDec:IncCounti|counter[2] ),
	.cout(\IncDec:IncCounti|counter[2]~62 ));
defparam \IncDec:IncCounti|counter[2]~I .operation_mode = "arithmetic";
defparam \IncDec:IncCounti|counter[2]~I .synch_mode = "on";
defparam \IncDec:IncCounti|counter[2]~I .register_cascade_mode = "off";
defparam \IncDec:IncCounti|counter[2]~I .sum_lutc_input = "cin";
defparam \IncDec:IncCounti|counter[2]~I .lut_mask = "C30C";
defparam \IncDec:IncCounti|counter[2]~I .output_mode = "reg_only";

cyclone_lcell \IncDec:IncCounti|counter[3]~I (
	.clk(clock),
	.datab(\IncDec:IncCounti|counter[3] ),
	.aclr(gnd),
	.sclr(sclrp),
	.cin(\IncDec:IncCounti|counter[2]~62 ),
	.regout(\IncDec:IncCounti|counter[3] ),
	.cout(\IncDec:IncCounti|counter[3]~66 ));
defparam \IncDec:IncCounti|counter[3]~I .operation_mode = "arithmetic";
defparam \IncDec:IncCounti|counter[3]~I .synch_mode = "on";
defparam \IncDec:IncCounti|counter[3]~I .register_cascade_mode = "off";
defparam \IncDec:IncCounti|counter[3]~I .sum_lutc_input = "cin";
defparam \IncDec:IncCounti|counter[3]~I .lut_mask = "3C3F";
defparam \IncDec:IncCounti|counter[3]~I .output_mode = "reg_only";

cyclone_lcell \IncDec:IncCounti|counter[4]~I (
	.clk(clock),
	.datab(\IncDec:IncCounti|counter[4] ),
	.aclr(gnd),
	.sclr(sclrp),
	.cin(\IncDec:IncCounti|counter[3]~66 ),
	.regout(\IncDec:IncCounti|counter[4] ),
	.cout(\IncDec:IncCounti|counter[4]~64 ));
defparam \IncDec:IncCounti|counter[4]~I .operation_mode = "arithmetic";
defparam \IncDec:IncCounti|counter[4]~I .synch_mode = "on";
defparam \IncDec:IncCounti|counter[4]~I .register_cascade_mode = "off";
defparam \IncDec:IncCounti|counter[4]~I .sum_lutc_input = "cin";
defparam \IncDec:IncCounti|counter[4]~I .lut_mask = "C30C";
defparam \IncDec:IncCounti|counter[4]~I .output_mode = "reg_only";

cyclone_lcell \IncDec:IncCounti|counter[5]~I (
	.clk(clock),
	.datad(\IncDec:IncCounti|counter[5] ),
	.aclr(gnd),
	.sclr(sclrp),
	.cin(\IncDec:IncCounti|counter[4]~64 ),
	.regout(\IncDec:IncCounti|counter[5] ));
defparam \IncDec:IncCounti|counter[5]~I .operation_mode = "normal";
defparam \IncDec:IncCounti|counter[5]~I .synch_mode = "on";
defparam \IncDec:IncCounti|counter[5]~I .register_cascade_mode = "off";
defparam \IncDec:IncCounti|counter[5]~I .sum_lutc_input = "cin";
defparam \IncDec:IncCounti|counter[5]~I .lut_mask = "0FF0";
defparam \IncDec:IncCounti|counter[5]~I .output_mode = "reg_only";

cyclone_lcell \SDelay:Delayi|result~464_I (
	.dataa(\IncDec:IncCounti|counter[5] ),
	.datab(\IncDec:IncCounti|counter[4] ),
	.datac(\IncDec:IncCounti|counter[1] ),
	.datad(\IncDec:IncCounti|counter[2] ),
	.combout(\SDelay:Delayi|result~464 ));
defparam \SDelay:Delayi|result~464_I .operation_mode = "normal";
defparam \SDelay:Delayi|result~464_I .synch_mode = "off";
defparam \SDelay:Delayi|result~464_I .register_cascade_mode = "off";
defparam \SDelay:Delayi|result~464_I .sum_lutc_input = "datac";