test.stp

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信 所用语言位verilog HDL

    </position_info>
    <signal_set global_temp="1" name="signal_set: 2007/11/07 11:02:39  #0">
      <clock name="sd_clk" polarity="posedge"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_trigger_nodes="0" sample_depth="16384" trigger_in_enable="yes" trigger_in_node="time1ms_out2" trigger_out_enable="no"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire connection_status="true" name="initial_block:inst9|send_cmd:inst4|cmd_num[0]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="initial_block:inst9|send_cmd:inst4|cmd_num[1]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="initial_block:inst9|send_cmd:inst4|cmd_num[2]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="initial_block:inst9|send_cmd:inst4|cmd_num[3]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sd2_cmd" tap_mode="classic" type="bidir pin"/>
          <wire connection_status="true" name="sd2_dat[0]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="sd2_dat[1]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="sd2_dat[2]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="sd2_dat[3]" tap_mode="classic" type="input pin"/>
        </trigger_input_vec>