get_response.v

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信 所用语言位verilog HDL

/******************************************

	函数名: get_response
	功  能：接收sd卡对各个命令的应答信号
	参  数：
	
*******************************************/

module get_response(num_read_en,
					enable,
					cmd_num,
					reset,
					data_in48,
					data_in136,
					flag,
					clk,
					right,
					wrong,
					initial_done,
					rca
					);

parameter len1=48;
parameter len2=136;
parameter pulsewide=1;
input   num_read_en,enable,reset,flag,clk;
input   [len1-1:0]data_in48;
input   [len2-1:0]data_in136;
input   [3:0]cmd_num;
output  right,wrong,initial_done;
output  [15:0]rca;

integer n;
reg     [3:0]temp_num;
reg     [len1-1:0]data48;
reg     [len2-1:0]data136;
reg     right,wrong,pulse_en,pulse,choose,initial_done;
reg     [15:0]rca;

always @(posedge num_read_en)
	begin
	if(num_read_en==1'b1)
		temp_num<=cmd_num;
	end
	
always @(posedge clk)
	begin
	if(!reset)
		begin
		data48<=48'b0;
		data136<=136'b0;
		end
	else
		begin
		if(flag==1'b1)
			begin
			if(temp_num!==4'b0100 && temp_num!==4'b0110)
				data48<=data_in48;
			else if(temp_num==4'b0100 || temp_num==4'b0110)
				data136<=data_in136;
			end
		else 
			begin
			data48<=48'b0;
			data136<=136'b0;
			end
		end
	end
	
always @(posedge clk)
	begin
	if(!reset)
		begin
		pulse_en<=1'b0;
		choose<=1'b0;
		n<=0;
		rca<=16'h0000;
		initial_done<=1'b0;
		end
	else
		begin
		if(enable==1'b1)
		    begin
			if(temp_num==1)                //复位命令cmd0
				begin
					if(n<49)
						begin
						pulse_en<=1'b0;
						n<=n+1;
						end
					else if(n<52)
						begin
						pulse_en<=1'b1;
						choose<=1'b0;
						n<=n+1;
						end
					else
						pulse_en<=1'b0;
				end
			else
				begin
				if(data48!==0 || data136!==0)      
					begin
					if(temp_num!==4'b1001)            //temp_num==10时单独处理
						pulse_en<=1'b1;

					case(temp_num)
						4'b0010: if(data48==48'h370000012083)   //cmd55的应答
				      				choose<=1'b0;
				   		 		else
				      				choose<=1'b1;
						4'b0011: if(data48==48'h3f80ff8000ff)   //acmd41的应答
									choose<=1'b0;
				   		 		else
				      				choose<=1'b1;	
						4'b0100: if(data136[135:128]==8'h3f)   //cmd2的应答03534453443031478000a20e5b007169
									choose<=1'b0;
				   		 		else
				      				choose<=1'b1;
						4'b0101: if(data48[47:40]==8'h03)	  //cmd3的应答
									begin
									rca<=data48[39:24];
									choose<=1'b0;
									end
				   		 		else
				      				choose<=1'b0;	
						4'b0110: if(data136[135:128]==8'h3f)   //cmd9
									choose<=1'b0;
				   		 		else
				      				choose<=1'b1;
						4'b0111: if(data48==48'h070000070075)	  //cmd7的应答
									choose<=1'b0;
				   		 		else
				      				choose<=1'b1;
						4'b1000: if(data48==48'h370000092033)   //cmd55的应答
									choose<=1'b0;
				   		 		else
				      				choose<=1'b1;
						4'b1001: if(data48==48'h0600000920b9 || data48==48'h0600000900dd)   //acmd6的应答
								begin
									initial_done<=1'b1;
									pulse_en<=1'b0;
									end
				   		 		else
									begin
				      				choose<=1'b1;
									pulse_en<=1'b1;
									end
					default
				    	choose<=1'b1;	
					endcase
					end
				end
			end
		else
			pulse_en<=1'b0;
		end
	end

always @(posedge clk)
	begin
	if(num_read_en==1'b1)
		begin
		if(choose==1'b0)
			right<=pulse;
		else
			wrong<=pulse;
		end
	else
		begin
		right<=1'b0;
		wrong<=1'b0;
		end
	end

confirmpulse pulse_gen( clk, enable, pulse_en, pulse, pulsewide );

endmodule