get_response.bsf

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信 所用语言位verilog HDL

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
	(rect 16 16 224 208)
	(text "get_response" (rect 5 0 71 12)(font "Arial" ))
	(text "inst" (rect 8 176 25 188)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "num_read_en" (rect 0 0 66 12)(font "Arial" ))
		(text "num_read_en" (rect 21 27 87 39)(font "Arial" ))
		(line (pt 0 32)(pt 16 32)(line_width 1))
	)
	(port
		(pt 0 48)
		(input)
		(text "enable" (rect 0 0 31 12)(font "Arial" ))
		(text "enable" (rect 21 43 52 55)(font "Arial" ))
		(line (pt 0 48)(pt 16 48)(line_width 1))
	)
	(port
		(pt 0 64)
		(input)
		(text "reset" (rect 0 0 24 12)(font "Arial" ))
		(text "reset" (rect 21 59 45 71)(font "Arial" ))
		(line (pt 0 64)(pt 16 64)(line_width 1))
	)
	(port
		(pt 0 80)
		(input)
		(text "flag" (rect 0 0 18 12)(font "Arial" ))
		(text "flag" (rect 21 75 39 87)(font "Arial" ))
		(line (pt 0 80)(pt 16 80)(line_width 1))
	)
	(port
		(pt 0 96)
		(input)
		(text "clk" (rect 0 0 14 12)(font "Arial" ))
		(text "clk" (rect 21 91 35 103)(font "Arial" ))
		(line (pt 0 96)(pt 16 96)(line_width 1))
	)
	(port
		(pt 0 112)
		(input)
		(text "data_in48[len1-1..0]" (rect 0 0 96 12)(font "Arial" ))
		(text "data_in48[len1-1..0]" (rect 21 107 117 119)(font "Arial" ))
		(line (pt 0 112)(pt 16 112)(line_width 3))
	)
	(port
		(pt 0 128)
		(input)
		(text "data_in136[len2-1..0]" (rect 0 0 102 12)(font "Arial" ))
		(text "data_in136[len2-1..0]" (rect 21 123 123 135)(font "Arial" ))
		(line (pt 0 128)(pt 16 128)(line_width 3))
	)
	(port
		(pt 0 144)
		(input)
		(text "cmd_num[3..0]" (rect 0 0 74 12)(font "Arial" ))
		(text "cmd_num[3..0]" (rect 21 139 95 151)(font "Arial" ))
		(line (pt 0 144)(pt 16 144)(line_width 3))
	)
	(port
		(pt 208 32)
		(output)
		(text "right" (rect 0 0 21 12)(font "Arial" ))
		(text "right" (rect 166 27 187 39)(font "Arial" ))
		(line (pt 208 32)(pt 192 32)(line_width 1))
	)
	(port
		(pt 208 48)
		(output)
		(text "wrong" (rect 0 0 28 12)(font "Arial" ))
		(text "wrong" (rect 159 43 187 55)(font "Arial" ))
		(line (pt 208 48)(pt 192 48)(line_width 1))
	)
	(port
		(pt 208 64)
		(output)
		(text "initial_done" (rect 0 0 54 12)(font "Arial" ))
		(text "initial_done" (rect 133 59 187 71)(font "Arial" ))
		(line (pt 208 64)(pt 192 64)(line_width 1))
	)
	(port
		(pt 208 80)
		(output)
		(text "rca[15..0]" (rect 0 0 47 12)(font "Arial" ))
		(text "rca[15..0]" (rect 140 75 187 87)(font "Arial" ))
		(line (pt 208 80)(pt 192 80)(line_width 3))
	)
	(parameter
		"len1"
		"48"
		""
	)
	(parameter
		"len2"
		"136"
		""
	)
	(parameter
		"pulsewide"
		"1"
		""
	)
	(drawing
		(rectangle (rect 16 16 192 176)(line_width 1))
	)
	(annotation_block (parameter)(rect 224 -64 324 16))
)