wipe_off_burr.v

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信 所用语言位verilog HDL

module wipe_off_burr(clk,rst,vp_en);
input rst,clk;
output vp_en;

reg vp_en;
integer i;

always @(posedge clk)
	begin
	if(!rst)
		begin
		i<=0;
		vp_en<=1'b0;
		end
	else
		begin
		if(i<12500000)
			i<=i+1;
		else
			vp_en<=1'b1;
		end
	end
endmodule