test.tan.rpt

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信 所用语言位verilog HDL

+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F484C8       ;      ;    ;             ;
; Timing Models                                         ; Preliminary        ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                          ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; sd_clk_in                    ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'sd_clk_in'                                                                                                                                                                                                                                                  ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------+-------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                               ; To                      ; From Clock ; To Clock  ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------+-------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 36.62 MHz ( period = 27.306 ns )                    ; sd_control:inst|block_num[9]~reg0  ; sd_control:inst|cmd[43] ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.761 ns                ;
; N/A                                     ; 37.11 MHz ( period = 26.944 ns )                    ; sd_control:inst|block_num[16]~reg0 ; sd_control:inst|cmd[43] ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.588 ns                ;
; N/A                                     ; 37.20 MHz ( period = 26.884 ns )                    ; sd_control:inst|block_num[1]~reg0  ; sd_control:inst|cmd[43] ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.550 ns                ;
; N/A                                     ; 37.29 MHz ( period = 26.820 ns )                    ; sd_control:inst|block_num[5]~reg0  ; sd_control:inst|cmd[43] ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.518 ns                ;
; N/A                                     ; 37.43 MHz ( period = 26.716 ns )                    ; sd_control:inst|block_num[6]~reg0  ; sd_control:inst|cmd[43] ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.466 ns                ;
; N/A                                     ; 37.59 MHz ( period = 26.600 ns )                    ; sd_control:inst|block_num[9]~reg0  ; sd_control:inst|cmd[25] ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.409 ns                ;
; N/A                                     ; 37.59 MHz ( period = 26.600 ns )                    ; sd_control:inst|block_num[9]~reg0  ; sd_control:inst|cmd[26] ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.409 ns                ;
; N/A                                     ; 37.59 MHz ( period = 26.600 ns )                    ; sd_control:inst|block_num[9]~reg0  ; sd_control:inst|cmd[27] ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.409 ns                ;
; N/A                                     ; 37.59 MHz ( period = 26.600 ns )                    ; sd_control:inst|block_num[9]~reg0  ; sd_control:inst|cmd[28] ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.409 ns                ;
; N/A                                     ; 37.59 MHz ( period = 26.600 ns )                    ; sd_control:inst|block_num[9]~reg0  ; sd_control:inst|cmd[29] ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.409 ns                ;
; N/A                                     ; 37.59 MHz ( period = 26.600 ns )                    ; sd_control:inst|block_num[9]~reg0  ; sd_control:inst|cmd[30] ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.409 ns                ;
; N/A                                     ; 37.59 MHz ( period = 26.600 ns )                    ; sd_control:inst|block_num[9]~reg0  ; sd_control:inst|cmd[31] ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.409 ns                ;
; N/A                                     ; 37.59 MHz ( period = 26.600 ns )                    ; sd_control:inst|block_num[9]~reg0  ; sd_control:inst|cmd[32] ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.409 ns                ;
; N/A                                     ; 37.59 MHz ( period = 26.600 ns )                    ; sd_control:inst|block_num[9]~reg0  ; sd_control:inst|cmd[33] ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.409 ns                ;
; N/A                                     ; 37.59 MHz ( period = 26.600 ns )                    ; sd_control:inst|block_num[9]~reg0  ; sd_control:inst|cmd[34] ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.409 ns                ;
; N/A                                     ; 37.59 MHz ( period = 26.600 ns )                    ; sd_control:inst|block_num[9]~reg0  ; sd_control:inst|cmd[35] ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.409 ns                ;
; N/A                                     ; 37.59 MHz ( period = 26.600 ns )                    ; sd_control:inst|block_num[9]~reg0  ; sd_control:inst|cmd[36] ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.409 ns                ;
; N/A                                     ; 37.59 MHz ( period = 26.600 ns )                    ; sd_control:inst|block_num[9]~reg0  ; sd_control:inst|cmd[37] ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.409 ns                ;
; N/A                                     ; 37.59 MHz ( period = 26.600 ns )                    ; sd_control:inst|block_num[9]~reg0  ; sd_control:inst|cmd[38] ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.409 ns                ;
; N/A                                     ; 37.59 MHz ( period = 26.600 ns )                    ; sd_control:inst|block_num[9]~reg0  ; sd_control:inst|cmd[39] ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.409 ns                ;
; N/A                                     ; 37.76 MHz ( period = 26.486 ns )                    ; sd_control:inst|block_num[9]~reg0  ; sd_control:inst|cmd[1]  ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.360 ns                ;
; N/A                                     ; 37.76 MHz ( period = 26.486 ns )                    ; sd_control:inst|block_num[9]~reg0  ; sd_control:inst|cmd[2]  ; sd_clk_in  ; sd_clk_in ; None                        ; None                      ; 7.360 ns                ;