send_cmd.v

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信 所用语言位verilog HDL

/*******************************************

	函数名：send_cmd
	功  能：发送sd卡初始化工程中的命令
	参  数：enable 可以利用time1ms_fg控制
			reset 可以利用powerup_fg控制
	
********************************************/

module send_cmd(clk,
				enable,
				right,
				wrong,
				cmd_data,
				cmd_num,
				en,
				crc_en,
				datatemp,
				crcfini,
				data47,
				rca
				);

parameter len=48;
input    clk,enable,right,wrong,crcfini;
input    [len-2:0]data47;
input    [15:0]rca;
output   [len-1:0]cmd_data;
output   [3:0]cmd_num;
output   en,crc_en;
output   [39:0]datatemp;
reg      [len-1:0]cmd_data;
reg      [3:0]cmd_num;
reg      en,en_fg,crc_en,crcflag;
reg      [5:0]cout;
reg      [39:0]datatemp;

always @(posedge clk )
		begin
		if(!enable)
			begin
			cmd_num<=4'b0000;
			cout<=6'b000000;
			crcflag<=1'b0;
			cmd_data<=48'h0000000000;
			en<=1'b0;
			en_fg<=1'b0;
			end
	    else					
			begin
			if(crcfini==1'b1)
				begin
				crcflag<=1'b1;
				cmd_data[47:1]<=data47;
				cmd_data[0]<=1'b1;
				en<=1'b1;
				en_fg<=1'b0;
				end
			else if(crcflag==1'b1)
				begin
				if(cout>49)
					begin
					en<=1'b0;
					cout<=6'b000000;
					crcflag<=1'b0;
					end					
				else
					cout<=cout+6'b000001;
				end
			else if(en==1'b0)
				begin
				if(right==1'b1 && wrong==1'b0)
					begin
					en_fg<=1'b1;
					cout<=6'b000000;
					cmd_num<=cmd_num+4'b0001;
					end
				else if(right==1'b0 && wrong==1'b1)
					begin
					en_fg<=1'b1;
					cout<=6'b000000;
					if(cmd_num==4'b0011 || cmd_num==4'b1001)
						cmd_num<=cmd_num-4'b0001;
					end
				end		
			end
		end

always @(posedge clk)
	begin
	if(!enable)
		begin
		crc_en<=1'b0;
		datatemp<=40'h0000000000;
		end
	else
		begin
		if(crcfini==1'b1)
			crc_en<=1'b0;
		else if(en_fg==1'b1)
			begin
			case(cmd_num)
			4'b0001:    begin
						datatemp<=40'h4000000000;//95; //cmd0
						crc_en<=1'b1;
						end
			4'b0010:    begin
						datatemp<=40'h7700000000;//65; //cmd55
						crc_en<=1'b1;
						end
			4'b0011:    begin
						datatemp<=40'h6900ff8000;//85;     //acmd41
						crc_en<=1'b1;
						end
			4'b0100:    begin
						datatemp<=40'h4200000000;//4d;//cmd2  //
						crc_en<=1'b1;
						end
			4'b0101:    begin
						datatemp<=40'h4300000000;//21; //cmd3   //
						crc_en<=1'b1;
						end
			4'b0110:    begin
						datatemp[39:32]<=8'h49;//d3;  //cmd9
						datatemp[31:16]<=rca;
						datatemp[15:0]<=16'h0000;
						crc_en<=1'b1;
						end
			4'b0111:    begin
						datatemp[39:32]<=8'h47;//ff;  //cmd7
						datatemp[31:16]<=rca;
						datatemp[15:0]<=16'h0000;
						crc_en<=1'b1;
						end
			4'b1000:    begin
						datatemp[39:32]<=8'h77;//19;     //cmd55
						datatemp[31:16]<=rca;
						datatemp[15:0]<=16'h0000;
						crc_en<=1'b1;
						end
			4'b1001:    begin
						datatemp<=40'h4600000002;//cb; //acmd6
						crc_en<=1'b1;
						end
			default:    datatemp<=40'h000000000000;
			endcase
			end
		end
	end	

endmodule