fadder4.fit.rpt
来自「VHDL实现四位全加器」· RPT 代码 · 共 642 行 · 第 1/5 页
RPT
642 行
+---------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 8.00) ; Number of LABs (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
+---------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 5.00) ; Number of LABs (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 9.00) ; Number of LABs (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
+---------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Active Serial ;
; Error detection CRC ; Off ;
; ASDO,nCSO ; As input tri-stated ;
; Reserve all unused pins ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+----------------------------+
; Advanced Data - General ;
+--------------------+-------+
; Name ; Value ;
+--------------------+-------+
; Status Code ; 0 ;
; Desired User Slack ; 0 ;
; Fit Attempts ; 1 ;
+--------------------+-------+
+---------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation ;
+--------------------------------------------------------------------------------+------------+
; Name ; Value ;
+--------------------------------------------------------------------------------+------------+
; Auto Fit Point 1 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 0 ;
; Mid Slack - Fit Attempt 1 ; 2147483639 ;
; Internal Atom Count - Fit Attempt 1 ; 9 ;
; LE/ALM Count - Fit Attempt 1 ; 9 ;
; LAB Count - Fit Attempt 1 ; 2 ;
; Outputs per Lab - Fit Attempt 1 ; 2.500 ;
; Inputs per LAB - Fit Attempt 1 ; 4.500 ;
; Global Inputs per LAB - Fit Attempt 1 ; 0.000 ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'un-route combination' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'global control signals' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:2 ;
; LEs in Chains - Fit Attempt 1 ; 0 ;
; LEs in Long Chains - Fit Attempt 1 ; 0 ;
; LABs with Chains - Fit Attempt 1 ; 0 ;
; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;
; Time - Fit Attempt 1 ; 0 ;
+--------------------------------------------------------------------------------+------------+
+-------------------------------------------------+
; Advanced Data - Placement ;
+------------------------------------+------------+
; Name ; Value ;
+------------------------------------+------------+
; Auto Fit Point 2 - Fit Attempt 1 ; ff ;
; Auto Fit Point 4 - Fit Attempt 1 ; ff ;
; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 0 ;
; Mid Slack - Fit Atte⌨️ 快捷键说明
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