dds.qsf

利用VHDL语言实现在

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		dds_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:06:07  FEBRUARY 06, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION "6.0 SP1"
set_global_assignment -name MIF_FILE sin7.mif
set_global_assignment -name VHDL_FILE adder7b.vhd
set_global_assignment -name VHDL_FILE fangbo.vhd
set_global_assignment -name VHDL_FILE ps7.vhd
set_global_assignment -name VHDL_FILE reg7b.vhd
set_global_assignment -name VHDL_FILE dds.vhd
set_global_assignment -name VHDL_FILE SIN_ROM.VHD
set_global_assignment -name VECTOR_WAVEFORM_FILE dds.vwf
set_global_assignment -name VHDL_FILE pl_dpsk2.vhd
set_global_assignment -name VHDL_FILE DDS1.VHD

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_28 -to CLK
set_location_assignment PIN_167 -to dc_out
set_location_assignment PIN_240 -to ls
set_location_assignment PIN_136 -to dds_out[7]
set_location_assignment PIN_135 -to dds_out[6]
set_location_assignment PIN_134 -to dds_out[5]
set_location_assignment PIN_133 -to dds_out[4]
set_location_assignment PIN_132 -to dds_out[3]
set_location_assignment PIN_128 -to dds_out[2]
set_location_assignment PIN_41 -to dds_out[1]
set_location_assignment PIN_21 -to dds_out[0]

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE PQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY DDS
set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C12Q240C8

# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF