dds.map.eqn

利用VHDL语言实现在

-- Copyright (C) 1991-2005 Altera Corporation
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--K1_q_a[0] is DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
K1_q_a[0]_PORT_A_address = BUS(~GND, C1L6, G2_DOUT[2], G2_DOUT[3], G2_DOUT[4], G2_DOUT[5], G2_DOUT[6]);
K1_q_a[0]_PORT_A_address_reg = DFFE(K1_q_a[0]_PORT_A_address, K1_q_a[0]_clock_0, , , );
K1_q_a[0]_clock_0 = CLK;
K1_q_a[0]_PORT_A_data_out = MEMORY(, , K1_q_a[0]_PORT_A_address_reg, , , , , , K1_q_a[0]_clock_0, , , , , );
K1_q_a[0]_PORT_A_data_out_reg = DFFE(K1_q_a[0]_PORT_A_data_out, K1_q_a[0]_clock_0, , , );
K1_q_a[0] = K1_q_a[0]_PORT_A_data_out_reg[0];


--K1_q_a[1] is DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
K1_q_a[1]_PORT_A_address = BUS(~GND, C1L6, G2_DOUT[2], G2_DOUT[3], G2_DOUT[4], G2_DOUT[5], G2_DOUT[6]);
K1_q_a[1]_PORT_A_address_reg = DFFE(K1_q_a[1]_PORT_A_address, K1_q_a[1]_clock_0, , , );
K1_q_a[1]_clock_0 = CLK;
K1_q_a[1]_PORT_A_data_out = MEMORY(, , K1_q_a[1]_PORT_A_address_reg, , , , , , K1_q_a[1]_clock_0, , , , , );
K1_q_a[1]_PORT_A_data_out_reg = DFFE(K1_q_a[1]_PORT_A_data_out, K1_q_a[1]_clock_0, , , );
K1_q_a[1] = K1_q_a[1]_PORT_A_data_out_reg[0];


--K1_q_a[2] is DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
K1_q_a[2]_PORT_A_address = BUS(~GND, C1L6, G2_DOUT[2], G2_DOUT[3], G2_DOUT[4], G2_DOUT[5], G2_DOUT[6]);
K1_q_a[2]_PORT_A_address_reg = DFFE(K1_q_a[2]_PORT_A_address, K1_q_a[2]_clock_0, , , );
K1_q_a[2]_clock_0 = CLK;
K1_q_a[2]_PORT_A_data_out = MEMORY(, , K1_q_a[2]_PORT_A_address_reg, , , , , , K1_q_a[2]_clock_0, , , , , );
K1_q_a[2]_PORT_A_data_out_reg = DFFE(K1_q_a[2]_PORT_A_data_out, K1_q_a[2]_clock_0, , , );
K1_q_a[2] = K1_q_a[2]_PORT_A_data_out_reg[0];


--K1_q_a[3] is DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
K1_q_a[3]_PORT_A_address = BUS(~GND, C1L6, G2_DOUT[2], G2_DOUT[3], G2_DOUT[4], G2_DOUT[5], G2_DOUT[6]);
K1_q_a[3]_PORT_A_address_reg = DFFE(K1_q_a[3]_PORT_A_address, K1_q_a[3]_clock_0, , , );
K1_q_a[3]_clock_0 = CLK;
K1_q_a[3]_PORT_A_data_out = MEMORY(, , K1_q_a[3]_PORT_A_address_reg, , , , , , K1_q_a[3]_clock_0, , , , , );
K1_q_a[3]_PORT_A_data_out_reg = DFFE(K1_q_a[3]_PORT_A_data_out, K1_q_a[3]_clock_0, , , );
K1_q_a[3] = K1_q_a[3]_PORT_A_data_out_reg[0];


--K1_q_a[4] is DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
K1_q_a[4]_PORT_A_address = BUS(~GND, C1L6, G2_DOUT[2], G2_DOUT[3], G2_DOUT[4], G2_DOUT[5], G2_DOUT[6]);
K1_q_a[4]_PORT_A_address_reg = DFFE(K1_q_a[4]_PORT_A_address, K1_q_a[4]_clock_0, , , );
K1_q_a[4]_clock_0 = CLK;
K1_q_a[4]_PORT_A_data_out = MEMORY(, , K1_q_a[4]_PORT_A_address_reg, , , , , , K1_q_a[4]_clock_0, , , , , );
K1_q_a[4]_PORT_A_data_out_reg = DFFE(K1_q_a[4]_PORT_A_data_out, K1_q_a[4]_clock_0, , , );
K1_q_a[4] = K1_q_a[4]_PORT_A_data_out_reg[0];


--K1_q_a[5] is DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
K1_q_a[5]_PORT_A_address = BUS(~GND, C1L6, G2_DOUT[2], G2_DOUT[3], G2_DOUT[4], G2_DOUT[5], G2_DOUT[6]);
K1_q_a[5]_PORT_A_address_reg = DFFE(K1_q_a[5]_PORT_A_address, K1_q_a[5]_clock_0, , , );
K1_q_a[5]_clock_0 = CLK;
K1_q_a[5]_PORT_A_data_out = MEMORY(, , K1_q_a[5]_PORT_A_address_reg, , , , , , K1_q_a[5]_clock_0, , , , , );
K1_q_a[5]_PORT_A_data_out_reg = DFFE(K1_q_a[5]_PORT_A_data_out, K1_q_a[5]_clock_0, , , );
K1_q_a[5] = K1_q_a[5]_PORT_A_data_out_reg[0];


--K1_q_a[6] is DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
K1_q_a[6]_PORT_A_address = BUS(~GND, C1L6, G2_DOUT[2], G2_DOUT[3], G2_DOUT[4], G2_DOUT[5], G2_DOUT[6]);
K1_q_a[6]_PORT_A_address_reg = DFFE(K1_q_a[6]_PORT_A_address, K1_q_a[6]_clock_0, , , );
K1_q_a[6]_clock_0 = CLK;
K1_q_a[6]_PORT_A_data_out = MEMORY(, , K1_q_a[6]_PORT_A_address_reg, , , , , , K1_q_a[6]_clock_0, , , , , );
K1_q_a[6]_PORT_A_data_out_reg = DFFE(K1_q_a[6]_PORT_A_data_out, K1_q_a[6]_clock_0, , , );
K1_q_a[6] = K1_q_a[6]_PORT_A_data_out_reg[0];


--K1_q_a[7] is DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
K1_q_a[7]_PORT_A_address = BUS(~GND, C1L6, G2_DOUT[2], G2_DOUT[3], G2_DOUT[4], G2_DOUT[5], G2_DOUT[6]);
K1_q_a[7]_PORT_A_address_reg = DFFE(K1_q_a[7]_PORT_A_address, K1_q_a[7]_clock_0, , , );
K1_q_a[7]_clock_0 = CLK;
K1_q_a[7]_PORT_A_data_out = MEMORY(, , K1_q_a[7]_PORT_A_address_reg, , , , , , K1_q_a[7]_clock_0, , , , , );
K1_q_a[7]_PORT_A_data_out_reg = DFFE(K1_q_a[7]_PORT_A_data_out, K1_q_a[7]_clock_0, , , );
K1_q_a[7] = K1_q_a[7]_PORT_A_data_out_reg[0];


--D1_y is PL_DPSK2:u2|y
--operation mode is normal

D1_y_lut_out = D1_xx1 $ D1_xx2;
D1_y = DFFEAS(D1_y_lut_out, CLK, VCC, , D1L91, , , , );


--C1_q[0] is DDS1:u1|q[0]
--operation mode is arithmetic

C1_q[0]_lut_out = !C1_q[0];
C1_q[0] = DFFEAS(C1_q[0]_lut_out, CLK, VCC, , , , , , );

--C1L5 is DDS1:u1|q[0]~78
--operation mode is arithmetic

C1L5 = CARRY(C1_q[0]);


--C1_q[1] is DDS1:u1|q[1]
--operation mode is arithmetic

C1_q[1]_carry_eqn = C1L5;
C1_q[1]_lut_out = C1_q[1] $ (C1_q[1]_carry_eqn);
C1_q[1] = DFFEAS(C1_q[1]_lut_out, CLK, VCC, , , , , , );

--C1L8 is DDS1:u1|q[1]~82
--operation mode is arithmetic

C1L8 = CARRY(!C1L5 # !C1_q[1]);


--C1_q[2] is DDS1:u1|q[2]
--operation mode is arithmetic

C1_q[2]_carry_eqn = C1L8;
C1_q[2]_lut_out = C1_q[2] $ (!C1_q[2]_carry_eqn);
C1_q[2] = DFFEAS(C1_q[2]_lut_out, CLK, VCC, , , , , , );

--C1L01 is DDS1:u1|q[2]~86
--operation mode is arithmetic

C1L01 = CARRY(C1_q[2] & (!C1L8));


--C1_q[3] is DDS1:u1|q[3]
--operation mode is arithmetic

C1_q[3]_carry_eqn = C1L01;
C1_q[3]_lut_out = C1_q[3] $ (C1_q[3]_carry_eqn);
C1_q[3] = DFFEAS(C1_q[3]_lut_out, CLK, VCC, , , , , , );

--C1L21 is DDS1:u1|q[3]~90
--operation mode is arithmetic

C1L21 = CARRY(!C1L01 # !C1_q[3]);


--C1_q[4] is DDS1:u1|q[4]
--operation mode is arithmetic

C1_q[4]_carry_eqn = C1L21;
C1_q[4]_lut_out = C1_q[4] $ (!C1_q[4]_carry_eqn);
C1_q[4] = DFFEAS(C1_q[4]_lut_out, CLK, VCC, , , , , , );

--C1L41 is DDS1:u1|q[4]~94
--operation mode is arithmetic

C1L41 = CARRY(C1_q[4] & (!C1L21));


--C1_q[5] is DDS1:u1|q[5]
--operation mode is arithmetic

C1_q[5]_carry_eqn = C1L41;
C1_q[5]_lut_out = C1_q[5] $ (C1_q[5]_carry_eqn);
C1_q[5] = DFFEAS(C1_q[5]_lut_out, CLK, VCC, , , , , , );

--C1L61 is DDS1:u1|q[5]~98
--operation mode is arithmetic

C1L61 = CARRY(!C1L41 # !C1_q[5]);


--C1_q[6] is DDS1:u1|q[6]
--operation mode is arithmetic

C1_q[6]_carry_eqn = C1L61;
C1_q[6]_lut_out = C1_q[6] $ (!C1_q[6]_carry_eqn);
C1_q[6] = DFFEAS(C1_q[6]_lut_out, CLK, VCC, , , , , , );

--C1L81 is DDS1:u1|q[6]~102
--operation mode is arithmetic

C1L81 = CARRY(C1_q[6] & (!C1L61));


--C1_q[7] is DDS1:u1|q[7]
--operation mode is arithmetic

C1_q[7]_carry_eqn = C1L81;
C1_q[7]_lut_out = C1_q[7] $ (C1_q[7]_carry_eqn);
C1_q[7] = DFFEAS(C1_q[7]_lut_out, CLK, VCC, , , , , , );

--C1L02 is DDS1:u1|q[7]~106
--operation mode is arithmetic

C1L02 = CARRY(!C1L81 # !C1_q[7]);


--C1_q[8] is DDS1:u1|q[8]
--operation mode is normal

C1_q[8]_carry_eqn = C1L02;
C1_q[8]_lut_out = C1_q[8] $ (!C1_q[8]_carry_eqn);
C1_q[8] = DFFEAS(C1_q[8]_lut_out, CLK, VCC, , , , , , );


--B1_q is ps7:u0|q
--operation mode is normal

B1_q_lut_out = !B1_c3;
B1_q = DFFEAS(B1_q_lut_out, !C1_q[8], VCC, , , B1L5, ls, , );


--G2_DOUT[2] is DDS1:u1|REG7B:u5|DOUT[2]
--operation mode is normal

G2_DOUT[2]_lut_out = C1_q[1];
G2_DOUT[2] = DFFEAS(G2_DOUT[2]_lut_out, CLK, VCC, , , , , , );


--G2_DOUT[3] is DDS1:u1|REG7B:u5|DOUT[3]
--operation mode is normal

G2_DOUT[3]_lut_out = C1_q[2];
G2_DOUT[3] = DFFEAS(G2_DOUT[3]_lut_out, CLK, VCC, , , , , , );


--G2_DOUT[4] is DDS1:u1|REG7B:u5|DOUT[4]
--operation mode is normal

G2_DOUT[4]_lut_out = C1_q[3];
G2_DOUT[4] = DFFEAS(G2_DOUT[4]_lut_out, CLK, VCC, , , , , , );


--G2_DOUT[5] is DDS1:u1|REG7B:u5|DOUT[5]
--operation mode is normal

G2_DOUT[5]_lut_out = C1_q[4];
G2_DOUT[5] = DFFEAS(G2_DOUT[5]_lut_out, CLK, VCC, , , , , , );


--G2_DOUT[6] is DDS1:u1|REG7B:u5|DOUT[6]
--operation mode is normal

G2_DOUT[6]_lut_out = C1_P7B[6] $ C1_q[5];
G2_DOUT[6] = DFFEAS(G2_DOUT[6]_lut_out, CLK, VCC, , , , , , );


--D1_xx1 is PL_DPSK2:u2|xx1
--operation mode is normal

D1_xx1_lut_out = E1_y;
D1_xx1 = DFFEAS(D1_xx1_lut_out, CLK, VCC, , !D1L81, , , , );


--D1_xx2 is PL_DPSK2:u2|xx2
--operation mode is normal

D1_xx2_lut_out = D1_xx1;
D1_xx2 = DFFEAS(D1_xx2_lut_out, CLK, VCC, , !D1L81, , , , );


--D1_q[1] is PL_DPSK2:u2|q[1]
--operation mode is arithmetic

D1_q[1]_lut_out = D1_q[1] $ C1_q[0];
D1_q[1] = DFFEAS(D1_q[1]_lut_out, CLK, VCC, , , D1L81, , , D1L61);

--D1L3 is PL_DPSK2:u2|q[1]~221
--operation mode is arithmetic

D1L3 = CARRY(D1_q[1] & C1_q[0]);


--D1_q[2] is PL_DPSK2:u2|q[2]
--operation mode is arithmetic

D1_q[2]_carry_eqn = D1L3;
D1_q[2]_lut_out = D1_q[2] $ (D1_q[2]_carry_eqn);
D1_q[2] = DFFEAS(D1_q[2]_lut_out, CLK, VCC, , , ~GND, , , D1L61);

--D1L5 is PL_DPSK2:u2|q[2]~225
--operation mode is arithmetic