dds.map.summary

来自「利用VHDL语言实现在」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Mon Jun 25 10:41:32 2007
Quartus II Version : 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
Revision Name : dds
Top-level Entity Name : DDS
Family : Cyclone
Total logic elements : 43
Total pins : 21
Total virtual pins : 0
Total memory bits : 1,024
Total PLLs : 0