reset.map.summary

来自「异步复位同步释放的复位信号处理逻辑代码.Verilog编写!很好用.在EP1C6」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Fri Apr 25 01:00:51 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : reset
Top-level Entity Name : reset
Family : Cyclone
Total logic elements : 2
Total pins : 3
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : N/A until Partition Merge
Total PLLs : 0
Total DLLs : N/A until Partition Merge